[llvm] [AMDGPU][NFCI] Declare offset0/1 operands to be i64. (PR #100560)
Ivan Kosarev via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 25 05:49:58 PDT 2024
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@@ -1270,8 +1270,8 @@ bool AMDGPUDAGToDAGISel::SelectDSReadWrite2(SDValue Addr, SDValue &Base,
// (add n0, c0)
if (isDSOffset2Legal(N0, OffsetValue0, OffsetValue1, Size)) {
Base = N0;
- Offset0 = CurDAG->getTargetConstant(OffsetValue0 / Size, DL, MVT::i8);
- Offset1 = CurDAG->getTargetConstant(OffsetValue1 / Size, DL, MVT::i8);
+ Offset0 = CurDAG->getTargetConstant(OffsetValue0 / Size, DL, MVT::i64);
+ Offset1 = CurDAG->getTargetConstant(OffsetValue1 / Size, DL, MVT::i64);
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kosarev wrote:
My thinking is, if we ever use unsigned constants employing all 32 bits, then we would be having the same problem with them. And they are stored as 64-bit ints anyway.
https://github.com/llvm/llvm-project/pull/100560
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