[llvm] [RISCV][GlobalISel] Legalize Scalable Vector Loads and Stores (PR #84965)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 23 09:33:28 PDT 2024
================
@@ -265,7 +266,23 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
.legalForTypesWithMemDesc({{s32, p0, s8, 8},
{s32, p0, s16, 16},
{s32, p0, s32, 32},
- {p0, p0, sXLen, XLen}});
+ {p0, p0, sXLen, XLen},
+ {nxv2s8, p0, nxv2s8, 8},
----------------
michaelmaitland wrote:
Do we need to check `hasVInstructions`?
```
if (ST.hasVInstructions())
LoadStoreActions.legalForTypesWithMemDesc({...})
```
https://github.com/llvm/llvm-project/pull/84965
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