[llvm] [GISel][TableGen] Generate getRegBankFromRegClass (PR #99896)
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Mon Jul 22 09:55:49 PDT 2024
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git-clang-format --diff e9709899db7d4a8b1c36475e90e4a934335f3d95 a6dc08eab1328ec698b3eddecc939c736c1f4efb --extensions cpp,h -- llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.h llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp llvm/lib/Target/ARM/ARMRegisterBankInfo.h llvm/lib/Target/M68k/GISel/M68kRegisterBankInfo.cpp llvm/lib/Target/M68k/GISel/M68kRegisterBankInfo.h llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp llvm/lib/Target/Mips/MipsRegisterBankInfo.h llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h llvm/lib/Target/SPIRV/SPIRVRegisterBankInfo.cpp llvm/lib/Target/SPIRV/SPIRVRegisterBankInfo.h llvm/lib/Target/X86/GISel/X86RegisterBankInfo.cpp llvm/lib/Target/X86/GISel/X86RegisterBankInfo.h llvm/utils/TableGen/RegisterBankEmitter.cpp
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diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index eedc84f274..fb7ff08da6 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -306,7 +306,7 @@ void RegisterBankEmitter::emitBaseClassImplementation(
for (const auto &Bank : Banks)
for (const auto *RC : Bank.register_classes()) {
if (RC->EnumValue >= Entries.size())
- Entries.resize(RC->EnumValue+1);
+ Entries.resize(RC->EnumValue + 1);
Entry &E = Entries[RC->EnumValue];
E.RCIdName = RC->getIdName();
if (!E.RBIdName.empty()) {
@@ -328,9 +328,9 @@ void RegisterBankEmitter::emitBaseClassImplementation(
if (HasAmbigousOrMissingEntry)
OS << " constexpr uint32_t InvalidRegBankID = uint32_t("
<< TargetName + "::InvalidRegBankID) & " << BitMask << ";\n";
- unsigned TableSize = Entries.size() / ElemsPerWord + ((Entries.size() % ElemsPerWord) > 0);
- OS << " static const uint32_t RegClass2RegBank["
- << TableSize << "] = {\n";
+ unsigned TableSize =
+ Entries.size() / ElemsPerWord + ((Entries.size() % ElemsPerWord) > 0);
+ OS << " static const uint32_t RegClass2RegBank[" << TableSize << "] = {\n";
uint32_t Shift = 32 - BitSize;
bool First = true;
std::string TrailingComment;
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https://github.com/llvm/llvm-project/pull/99896
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