[llvm] [DAG] Support saturated truncate (PR #99418)

[David Green via llvm-commits]

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@@ -1274,6 +1274,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
       setOperationAction(ISD::AVGCEILU, VT, Legal);
       setOperationAction(ISD::ABDS, VT, Legal);
       setOperationAction(ISD::ABDU, VT, Legal);
+      setOperationAction(ISD::TRUNCATE_SSAT, VT, Legal);
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davemgreen wrote:

Is the intent to say that a `MVT::v8i16 -> MVT::v8i8` truncating saturate is legal? If so does it need to mark the `MVT::v8i16` or the `MVT::v8i8`, and what happens if it is a `MVT::v8i32 -> MVT::v8i8` or `MVT::v4i32 -> MVT::v4i8` truncate?

If the isOperationLegalOrCustom looks at SrcVT then we likely only need to mark `MVT::v8i16, MVT::v4i32, MVT::v2i64` as legal, but there should hopefully be tests for the other case mentioned above. Note that I don't think that v2i64->v2i32 is handled at the moment with our tablegen patterns because we don't have support for 64bit min/max. So hopefully they might be able to start working with this patch.

https://github.com/llvm/llvm-project/pull/99418