[llvm] [AArch64] Fix lowring error for masked load/store integer scalable ve… (PR #99354)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff 486d00eca6b6ab470e8324b52cdf9f32023c1c9a 4956512745a8ce4b8fe3309aa6743e8824e32905 --extensions cpp -- llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index b357d677ca..9ad287f8af 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -6941,7 +6941,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(SDNode *N, unsigned OpNo) {
   }
 
   assert(Mask.getValueType().getVectorMinNumElements() ==
-          StVal.getValueType().getVectorMinNumElements() &&
+             StVal.getValueType().getVectorMinNumElements() &&
          "Mask and data vectors should have the same number of elements");
   return DAG.getMaskedStore(MST->getChain(), dl, StVal, MST->getBasePtr(),
                             MST->getOffset(), Mask, MST->getMemoryVT(),

``````````

</details>


https://github.com/llvm/llvm-project/pull/99354