[llvm] [PowerPC] Add phony subregisters to cover the high half of the VSX registers. (PR #94628)

[Stefan Pintilie via llvm-commits]

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@@ -750,25 +750,21 @@ entry:
 define <2 x double> @testDoubleImm1(<2 x double> %a, double %b) {
 ; CHECK-64-LABEL: testDoubleImm1:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    # kill: def $f1 killed $f1 def $vsl1
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stefanp-ibm wrote:

> If the phony lane isn't alive at the COPY, I think it's ok we don't have the `implicit-def vsl1`.

I think that is what is happening here. I took a look at one of the smaller tests `combine-fneg.ll` to see and the MIR looks like this:
```
  liveins: $f1, $v2, $v3                                                                                                                                                                                        
    undef %3.sub_64:vsrc = COPY $f1                                                                                    
    %4:vsrc = XXPERMDI killed %3:vsrc, %3:vsrc, 0   // This is the only use of %3
```
The only reason we use the VSRC register is because that is the type of register that XXPERMDI requires. The other lane is never used and the value in `$f1` is just splatted into `%4`.

https://github.com/llvm/llvm-project/pull/94628