[llvm] [RISCV] vsetvl pseudo may cross inline asm without sideeffect (PR #97794)

[Kito Cheng via llvm-commits]

kito-cheng wrote:

> Maybe we can add a new inline asm constraint that will add implicit vl/vtype operands?

That sounds one possible direction, but need few more brainstorm :P

Two options in my mind so far:

1. Encoding correct VTYPE value in inline asm operand:
```
#include <riscv_vector.h>

void foo(int32_t *a, int32_t *b, int32_t *c, size_t vl){
   size_t avl = __riscv_vsetvl_e32m1(vl);
   vint32m1_t va, vb, vc;
   vb = __riscv_vle32_v_i32m1(b, avl);
   vc = __riscv_vle32_v_i32m1(c, avl);
   asm ("vadd.vv %0, %1, %2"
        : "=vr" (va)
        : "vr" (vb), "vr" (vc), "r"(avl), "VT"(ENCODING_VTYPE(SEW32, LMUL1))
        );

   __riscv_vse32_v_i32m1(a, va, avl);
}
```

But that means we need handle inline asm within vsetvli insertion.

2. Extend the syntax to allow the physical register appeared in the input operand:

```
#include <riscv_vector.h>

void foo(int32_t *a, int32_t *b, int32_t *c, size_t vl){
   size_t avl = __riscv_vsetvl_e32m1(vl);
   vint32m1_t va, vb, vc;
   vb = __riscv_vle32_v_i32m1(b, avl);
   vc = __riscv_vle32_v_i32m1(c, avl);
   asm ("vadd.vv %0, %1, %2"
        : "=vr" (va)
        : "vr" (vb), "vr" (vc), "r"(avl), "vtype");

   __riscv_vse32_v_i32m1(a, va, avl);
}
```




https://github.com/llvm/llvm-project/pull/97794