[llvm] [RISCV] Combine vp_strided_load with zero stride to scalar load + splat (PR #97798)

[Yeting Kuo via llvm-commits]

yetingk wrote:

> I think @yetingk is looking at doing this in RISCVCodeGenPrepare where we have access to IR's `isKnownNonZero`. We need that to handle the loop vectorized case where we only know the EVL is non-zero because of a branch in the loop preheader.

I had created a draft PR #98140. It's just a draft, since it's hard to create a splat with specific vl in IR level. I used riscv intrinsics vmv_v_x/vmv_v_f in this PR, but the implementation made fixed vector not benefit this optimization. 

https://github.com/llvm/llvm-project/pull/97798