[llvm] [AArch64][GlobalISel] Select SHL({Z|S}EXT, DUP Imm) into {U|S}HLL Imm (PR #96782)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 9 02:55:14 PDT 2024
https://github.com/chuongg3 updated https://github.com/llvm/llvm-project/pull/96782
>From f55d70bca7138624665da76d33eab9a962ffe70a Mon Sep 17 00:00:00 2001
From: Tuan Chuong Goh <chuong.goh at arm.com>
Date: Fri, 31 May 2024 15:32:07 +0000
Subject: [PATCH 1/2] [AArch64][NFC] Pre-commit tests for Shift Left Long
---
.../CodeGen/AArch64/neon-shift-left-long.ll | 238 ++++++++++++++----
1 file changed, 186 insertions(+), 52 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/neon-shift-left-long.ll b/llvm/test/CodeGen/AArch64/neon-shift-left-long.ll
index d10d551805a6b..3dcd23051ce52 100644
--- a/llvm/test/CodeGen/AArch64/neon-shift-left-long.ll
+++ b/llvm/test/CodeGen/AArch64/neon-shift-left-long.ll
@@ -1,56 +1,114 @@
-; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define <8 x i16> @test_sshll_v8i8(<8 x i8> %a) {
-; CHECK: test_sshll_v8i8:
-; CHECK: sshll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #3
+; CHECK-SD-LABEL: test_sshll_v8i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #3
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_sshll_v8i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: shl v0.8h, v0.8h, #3
+; CHECK-GI-NEXT: ret
%1 = sext <8 x i8> %a to <8 x i16>
%tmp = shl <8 x i16> %1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
ret <8 x i16> %tmp
}
define <4 x i32> @test_sshll_v4i16(<4 x i16> %a) {
-; CHECK: test_sshll_v4i16:
-; CHECK: sshll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #9
+; CHECK-SD-LABEL: test_sshll_v4i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #9
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_sshll_v4i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll v0.4s, v0.4h, #0
+; CHECK-GI-NEXT: shl v0.4s, v0.4s, #9
+; CHECK-GI-NEXT: ret
%1 = sext <4 x i16> %a to <4 x i32>
%tmp = shl <4 x i32> %1, <i32 9, i32 9, i32 9, i32 9>
ret <4 x i32> %tmp
}
define <2 x i64> @test_sshll_v2i32(<2 x i32> %a) {
-; CHECK: test_sshll_v2i32:
-; CHECK: sshll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #19
+; CHECK-SD-LABEL: test_sshll_v2i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sshll v0.2d, v0.2s, #19
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_sshll_v2i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll v0.2d, v0.2s, #0
+; CHECK-GI-NEXT: shl v0.2d, v0.2d, #19
+; CHECK-GI-NEXT: ret
%1 = sext <2 x i32> %a to <2 x i64>
%tmp = shl <2 x i64> %1, <i64 19, i64 19>
ret <2 x i64> %tmp
}
define <8 x i16> @test_ushll_v8i8(<8 x i8> %a) {
-; CHECK: test_ushll_v8i8:
-; CHECK: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #3
+; CHECK-SD-LABEL: test_ushll_v8i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #3
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_ushll_v8i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: shl v0.8h, v0.8h, #3
+; CHECK-GI-NEXT: ret
%1 = zext <8 x i8> %a to <8 x i16>
%tmp = shl <8 x i16> %1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
ret <8 x i16> %tmp
}
define <4 x i32> @test_ushll_v4i16(<4 x i16> %a) {
-; CHECK: test_ushll_v4i16:
-; CHECK: ushll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #9
+; CHECK-SD-LABEL: test_ushll_v4i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #9
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_ushll_v4i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
+; CHECK-GI-NEXT: shl v0.4s, v0.4s, #9
+; CHECK-GI-NEXT: ret
%1 = zext <4 x i16> %a to <4 x i32>
%tmp = shl <4 x i32> %1, <i32 9, i32 9, i32 9, i32 9>
ret <4 x i32> %tmp
}
define <2 x i64> @test_ushll_v2i32(<2 x i32> %a) {
-; CHECK: test_ushll_v2i32:
-; CHECK: ushll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #19
+; CHECK-SD-LABEL: test_ushll_v2i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #19
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_ushll_v2i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #0
+; CHECK-GI-NEXT: shl v0.2d, v0.2d, #19
+; CHECK-GI-NEXT: ret
%1 = zext <2 x i32> %a to <2 x i64>
%tmp = shl <2 x i64> %1, <i64 19, i64 19>
ret <2 x i64> %tmp
}
define <8 x i16> @test_sshll2_v16i8(<16 x i8> %a) {
-; CHECK: test_sshll2_v16i8:
-; CHECK: sshll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #3
+; CHECK-SD-LABEL: test_sshll2_v16i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sshll2 v0.8h, v0.16b, #3
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_sshll2_v16i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll2 v0.8h, v0.16b, #0
+; CHECK-GI-NEXT: shl v0.8h, v0.8h, #3
+; CHECK-GI-NEXT: ret
%1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%2 = sext <8 x i8> %1 to <8 x i16>
%tmp = shl <8 x i16> %2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
@@ -58,8 +116,16 @@ define <8 x i16> @test_sshll2_v16i8(<16 x i8> %a) {
}
define <4 x i32> @test_sshll2_v8i16(<8 x i16> %a) {
-; CHECK: test_sshll2_v8i16:
-; CHECK: sshll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #9
+; CHECK-SD-LABEL: test_sshll2_v8i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sshll2 v0.4s, v0.8h, #9
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_sshll2_v8i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll2 v0.4s, v0.8h, #0
+; CHECK-GI-NEXT: shl v0.4s, v0.4s, #9
+; CHECK-GI-NEXT: ret
%1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%2 = sext <4 x i16> %1 to <4 x i32>
%tmp = shl <4 x i32> %2, <i32 9, i32 9, i32 9, i32 9>
@@ -67,8 +133,16 @@ define <4 x i32> @test_sshll2_v8i16(<8 x i16> %a) {
}
define <2 x i64> @test_sshll2_v4i32(<4 x i32> %a) {
-; CHECK: test_sshll2_v4i32:
-; CHECK: sshll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #19
+; CHECK-SD-LABEL: test_sshll2_v4i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sshll2 v0.2d, v0.4s, #19
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_sshll2_v4i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll2 v0.2d, v0.4s, #0
+; CHECK-GI-NEXT: shl v0.2d, v0.2d, #19
+; CHECK-GI-NEXT: ret
%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%2 = sext <2 x i32> %1 to <2 x i64>
%tmp = shl <2 x i64> %2, <i64 19, i64 19>
@@ -76,8 +150,16 @@ define <2 x i64> @test_sshll2_v4i32(<4 x i32> %a) {
}
define <8 x i16> @test_ushll2_v16i8(<16 x i8> %a) {
-; CHECK: test_ushll2_v16i8:
-; CHECK: ushll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #3
+; CHECK-SD-LABEL: test_ushll2_v16i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ushll2 v0.8h, v0.16b, #3
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_ushll2_v16i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll2 v0.8h, v0.16b, #0
+; CHECK-GI-NEXT: shl v0.8h, v0.8h, #3
+; CHECK-GI-NEXT: ret
%1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%2 = zext <8 x i8> %1 to <8 x i16>
%tmp = shl <8 x i16> %2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
@@ -85,8 +167,16 @@ define <8 x i16> @test_ushll2_v16i8(<16 x i8> %a) {
}
define <4 x i32> @test_ushll2_v8i16(<8 x i16> %a) {
-; CHECK: test_ushll2_v8i16:
-; CHECK: ushll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #9
+; CHECK-SD-LABEL: test_ushll2_v8i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ushll2 v0.4s, v0.8h, #9
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_ushll2_v8i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll2 v0.4s, v0.8h, #0
+; CHECK-GI-NEXT: shl v0.4s, v0.4s, #9
+; CHECK-GI-NEXT: ret
%1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%2 = zext <4 x i16> %1 to <4 x i32>
%tmp = shl <4 x i32> %2, <i32 9, i32 9, i32 9, i32 9>
@@ -94,8 +184,16 @@ define <4 x i32> @test_ushll2_v8i16(<8 x i16> %a) {
}
define <2 x i64> @test_ushll2_v4i32(<4 x i32> %a) {
-; CHECK: test_ushll2_v4i32:
-; CHECK: ushll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #19
+; CHECK-SD-LABEL: test_ushll2_v4i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ushll2 v0.2d, v0.4s, #19
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_ushll2_v4i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll2 v0.2d, v0.4s, #0
+; CHECK-GI-NEXT: shl v0.2d, v0.2d, #19
+; CHECK-GI-NEXT: ret
%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%2 = zext <2 x i32> %1 to <2 x i64>
%tmp = shl <2 x i64> %2, <i64 19, i64 19>
@@ -103,99 +201,135 @@ define <2 x i64> @test_ushll2_v4i32(<4 x i32> %a) {
}
define <8 x i16> @test_sshll_shl0_v8i8(<8 x i8> %a) {
-; CHECK: test_sshll_shl0_v8i8:
-; CHECK: sshll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0
+; CHECK-LABEL: test_sshll_shl0_v8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-NEXT: ret
%tmp = sext <8 x i8> %a to <8 x i16>
ret <8 x i16> %tmp
}
define <4 x i32> @test_sshll_shl0_v4i16(<4 x i16> %a) {
-; CHECK: test_sshll_shl0_v4i16:
-; CHECK: sshll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #0
+; CHECK-LABEL: test_sshll_shl0_v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sshll v0.4s, v0.4h, #0
+; CHECK-NEXT: ret
%tmp = sext <4 x i16> %a to <4 x i32>
ret <4 x i32> %tmp
}
define <2 x i64> @test_sshll_shl0_v2i32(<2 x i32> %a) {
-; CHECK: test_sshll_shl0_v2i32:
-; CHECK: sshll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #0
+; CHECK-LABEL: test_sshll_shl0_v2i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sshll v0.2d, v0.2s, #0
+; CHECK-NEXT: ret
%tmp = sext <2 x i32> %a to <2 x i64>
ret <2 x i64> %tmp
}
define <8 x i16> @test_ushll_shl0_v8i8(<8 x i8> %a) {
-; CHECK: test_ushll_shl0_v8i8:
-; CHECK: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0
+; CHECK-LABEL: test_ushll_shl0_v8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-NEXT: ret
%tmp = zext <8 x i8> %a to <8 x i16>
ret <8 x i16> %tmp
}
define <4 x i32> @test_ushll_shl0_v4i16(<4 x i16> %a) {
-; CHECK: test_ushll_shl0_v4i16:
-; CHECK: ushll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #0
+; CHECK-LABEL: test_ushll_shl0_v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushll v0.4s, v0.4h, #0
+; CHECK-NEXT: ret
%tmp = zext <4 x i16> %a to <4 x i32>
ret <4 x i32> %tmp
}
define <2 x i64> @test_ushll_shl0_v2i32(<2 x i32> %a) {
-; CHECK: test_ushll_shl0_v2i32:
-; CHECK: ushll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #0
+; CHECK-LABEL: test_ushll_shl0_v2i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushll v0.2d, v0.2s, #0
+; CHECK-NEXT: ret
%tmp = zext <2 x i32> %a to <2 x i64>
ret <2 x i64> %tmp
}
define <8 x i16> @test_sshll2_shl0_v16i8(<16 x i8> %a) {
-; CHECK: test_sshll2_shl0_v16i8:
-; CHECK: sshll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #0
+; CHECK-LABEL: test_sshll2_shl0_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sshll2 v0.8h, v0.16b, #0
+; CHECK-NEXT: ret
%1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%tmp = sext <8 x i8> %1 to <8 x i16>
ret <8 x i16> %tmp
}
define <4 x i32> @test_sshll2_shl0_v8i16(<8 x i16> %a) {
-; CHECK: test_sshll2_shl0_v8i16:
-; CHECK: sshll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #0
+; CHECK-LABEL: test_sshll2_shl0_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sshll2 v0.4s, v0.8h, #0
+; CHECK-NEXT: ret
%1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%tmp = sext <4 x i16> %1 to <4 x i32>
ret <4 x i32> %tmp
}
define <2 x i64> @test_sshll2_shl0_v4i32(<4 x i32> %a) {
-; CHECK: test_sshll2_shl0_v4i32:
-; CHECK: sshll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #0
+; CHECK-LABEL: test_sshll2_shl0_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sshll2 v0.2d, v0.4s, #0
+; CHECK-NEXT: ret
%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%tmp = sext <2 x i32> %1 to <2 x i64>
ret <2 x i64> %tmp
}
define <8 x i16> @test_ushll2_shl0_v16i8(<16 x i8> %a) {
-; CHECK: test_ushll2_shl0_v16i8:
-; CHECK: ushll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #0
+; CHECK-LABEL: test_ushll2_shl0_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushll2 v0.8h, v0.16b, #0
+; CHECK-NEXT: ret
%1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%tmp = zext <8 x i8> %1 to <8 x i16>
ret <8 x i16> %tmp
}
define <4 x i32> @test_ushll2_shl0_v8i16(<8 x i16> %a) {
-; CHECK: test_ushll2_shl0_v8i16:
-; CHECK: ushll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #0
+; CHECK-LABEL: test_ushll2_shl0_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushll2 v0.4s, v0.8h, #0
+; CHECK-NEXT: ret
%1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%tmp = zext <4 x i16> %1 to <4 x i32>
ret <4 x i32> %tmp
}
define <2 x i64> @test_ushll2_shl0_v4i32(<4 x i32> %a) {
-; CHECK: test_ushll2_shl0_v4i32:
-; CHECK: ushll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #0
+; CHECK-LABEL: test_ushll2_shl0_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushll2 v0.2d, v0.4s, #0
+; CHECK-NEXT: ret
%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%tmp = zext <2 x i32> %1 to <2 x i64>
ret <2 x i64> %tmp
}
define <8 x i16> @test_ushll_cmp(<8 x i8> %a, <8 x i8> %b) #0 {
-; CHECK: test_ushll_cmp:
-; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
-; CHECK-NEXT: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0
+; CHECK-SD-LABEL: test_ushll_cmp:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_ushll_cmp:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
+; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: shl v0.8h, v0.8h, #15
+; CHECK-GI-NEXT: sshr v0.8h, v0.8h, #15
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: ret
%cmp.i = icmp eq <8 x i8> %a, %b
%vcgtz.i.i = sext <8 x i1> %cmp.i to <8 x i8>
%vmovl.i.i.i = zext <8 x i8> %vcgtz.i.i to <8 x i16>
>From 7a424a53c33ad9bd7f3f5668c1426f83906ef1c8 Mon Sep 17 00:00:00 2001
From: Tuan Chuong Goh <chuong.goh at arm.com>
Date: Thu, 20 Jun 2024 12:40:51 +0000
Subject: [PATCH 2/2] [AArch64][GlobalISel] Select SHL(ZEXT, DUP imm) into
{U/S}HLL imm
---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 14 +++
.../CodeGen/AArch64/neon-shift-left-long.ll | 108 ++++++------------
2 files changed, 50 insertions(+), 72 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 1e06d5fdc7562..c082dbe93e4c1 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -7996,6 +7996,20 @@ def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
(SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
V128:$Rn, vecshiftR32Narrow:$imm)>;
+def : Pat<(shl (v8i16 (zext (v8i8 V64:$Rm))), (v8i16 (AArch64dup (i32 imm:$size)))),
+ (USHLLv8i8_shift V64:$Rm, (i32 imm:$size))>;
+def : Pat<(shl (v4i32 (zext (v4i16 V64:$Rm))), (v4i32 (AArch64dup (i32 imm:$size)))),
+ (USHLLv4i16_shift V64:$Rm, (i32 imm:$size))>;
+def : Pat<(shl (v2i64 (zext (v2i32 V64:$Rm))), (v2i64 (AArch64dup (i64 imm:$size)))),
+ (USHLLv2i32_shift V64:$Rm, (trunc_imm imm:$size))>;
+
+def : Pat<(shl (v8i16 (sext (v8i8 V64:$Rm))), (v8i16 (AArch64dup (i32 imm:$size)))),
+ (SSHLLv8i8_shift V64:$Rm, (i32 imm:$size))>;
+def : Pat<(shl (v4i32 (sext (v4i16 V64:$Rm))), (v4i32 (AArch64dup (i32 imm:$size)))),
+ (SSHLLv4i16_shift V64:$Rm, (i32 imm:$size))>;
+def : Pat<(shl (v2i64 (sext (v2i32 V64:$Rm))), (v2i64 (AArch64dup (i64 imm:$size)))),
+ (SSHLLv2i32_shift V64:$Rm, (trunc_imm imm:$size))>;
+
// Vector sign and zero extensions are implemented with SSHLL and USSHLL.
// Anyexts are implemented as zexts.
def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
diff --git a/llvm/test/CodeGen/AArch64/neon-shift-left-long.ll b/llvm/test/CodeGen/AArch64/neon-shift-left-long.ll
index 3dcd23051ce52..a06bc0856c9f1 100644
--- a/llvm/test/CodeGen/AArch64/neon-shift-left-long.ll
+++ b/llvm/test/CodeGen/AArch64/neon-shift-left-long.ll
@@ -3,96 +3,60 @@
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define <8 x i16> @test_sshll_v8i8(<8 x i8> %a) {
-; CHECK-SD-LABEL: test_sshll_v8i8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #3
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_sshll_v8i8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
-; CHECK-GI-NEXT: shl v0.8h, v0.8h, #3
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_sshll_v8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sshll v0.8h, v0.8b, #3
+; CHECK-NEXT: ret
%1 = sext <8 x i8> %a to <8 x i16>
%tmp = shl <8 x i16> %1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
ret <8 x i16> %tmp
}
define <4 x i32> @test_sshll_v4i16(<4 x i16> %a) {
-; CHECK-SD-LABEL: test_sshll_v4i16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #9
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_sshll_v4i16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sshll v0.4s, v0.4h, #0
-; CHECK-GI-NEXT: shl v0.4s, v0.4s, #9
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_sshll_v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sshll v0.4s, v0.4h, #9
+; CHECK-NEXT: ret
%1 = sext <4 x i16> %a to <4 x i32>
%tmp = shl <4 x i32> %1, <i32 9, i32 9, i32 9, i32 9>
ret <4 x i32> %tmp
}
define <2 x i64> @test_sshll_v2i32(<2 x i32> %a) {
-; CHECK-SD-LABEL: test_sshll_v2i32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: sshll v0.2d, v0.2s, #19
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_sshll_v2i32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sshll v0.2d, v0.2s, #0
-; CHECK-GI-NEXT: shl v0.2d, v0.2d, #19
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_sshll_v2i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sshll v0.2d, v0.2s, #19
+; CHECK-NEXT: ret
%1 = sext <2 x i32> %a to <2 x i64>
%tmp = shl <2 x i64> %1, <i64 19, i64 19>
ret <2 x i64> %tmp
}
define <8 x i16> @test_ushll_v8i8(<8 x i8> %a) {
-; CHECK-SD-LABEL: test_ushll_v8i8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #3
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_ushll_v8i8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-GI-NEXT: shl v0.8h, v0.8h, #3
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_ushll_v8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushll v0.8h, v0.8b, #3
+; CHECK-NEXT: ret
%1 = zext <8 x i8> %a to <8 x i16>
%tmp = shl <8 x i16> %1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
ret <8 x i16> %tmp
}
define <4 x i32> @test_ushll_v4i16(<4 x i16> %a) {
-; CHECK-SD-LABEL: test_ushll_v4i16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #9
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_ushll_v4i16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-GI-NEXT: shl v0.4s, v0.4s, #9
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_ushll_v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushll v0.4s, v0.4h, #9
+; CHECK-NEXT: ret
%1 = zext <4 x i16> %a to <4 x i32>
%tmp = shl <4 x i32> %1, <i32 9, i32 9, i32 9, i32 9>
ret <4 x i32> %tmp
}
define <2 x i64> @test_ushll_v2i32(<2 x i32> %a) {
-; CHECK-SD-LABEL: test_ushll_v2i32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #19
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_ushll_v2i32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #0
-; CHECK-GI-NEXT: shl v0.2d, v0.2d, #19
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_ushll_v2i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushll v0.2d, v0.2s, #19
+; CHECK-NEXT: ret
%1 = zext <2 x i32> %a to <2 x i64>
%tmp = shl <2 x i64> %1, <i64 19, i64 19>
ret <2 x i64> %tmp
@@ -106,8 +70,8 @@ define <8 x i16> @test_sshll2_v16i8(<16 x i8> %a) {
;
; CHECK-GI-LABEL: test_sshll2_v16i8:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sshll2 v0.8h, v0.16b, #0
-; CHECK-GI-NEXT: shl v0.8h, v0.8h, #3
+; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #3
; CHECK-GI-NEXT: ret
%1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%2 = sext <8 x i8> %1 to <8 x i16>
@@ -123,8 +87,8 @@ define <4 x i32> @test_sshll2_v8i16(<8 x i16> %a) {
;
; CHECK-GI-LABEL: test_sshll2_v8i16:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sshll2 v0.4s, v0.8h, #0
-; CHECK-GI-NEXT: shl v0.4s, v0.4s, #9
+; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: sshll v0.4s, v0.4h, #9
; CHECK-GI-NEXT: ret
%1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%2 = sext <4 x i16> %1 to <4 x i32>
@@ -140,8 +104,8 @@ define <2 x i64> @test_sshll2_v4i32(<4 x i32> %a) {
;
; CHECK-GI-LABEL: test_sshll2_v4i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sshll2 v0.2d, v0.4s, #0
-; CHECK-GI-NEXT: shl v0.2d, v0.2d, #19
+; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: sshll v0.2d, v0.2s, #19
; CHECK-GI-NEXT: ret
%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%2 = sext <2 x i32> %1 to <2 x i64>
@@ -157,8 +121,8 @@ define <8 x i16> @test_ushll2_v16i8(<16 x i8> %a) {
;
; CHECK-GI-LABEL: test_ushll2_v16i8:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ushll2 v0.8h, v0.16b, #0
-; CHECK-GI-NEXT: shl v0.8h, v0.8h, #3
+; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #3
; CHECK-GI-NEXT: ret
%1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%2 = zext <8 x i8> %1 to <8 x i16>
@@ -174,8 +138,8 @@ define <4 x i32> @test_ushll2_v8i16(<8 x i16> %a) {
;
; CHECK-GI-LABEL: test_ushll2_v8i16:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ushll2 v0.4s, v0.8h, #0
-; CHECK-GI-NEXT: shl v0.4s, v0.4s, #9
+; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #9
; CHECK-GI-NEXT: ret
%1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%2 = zext <4 x i16> %1 to <4 x i32>
@@ -191,8 +155,8 @@ define <2 x i64> @test_ushll2_v4i32(<4 x i32> %a) {
;
; CHECK-GI-LABEL: test_ushll2_v4i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ushll2 v0.2d, v0.4s, #0
-; CHECK-GI-NEXT: shl v0.2d, v0.2d, #19
+; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #19
; CHECK-GI-NEXT: ret
%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%2 = zext <2 x i32> %1 to <2 x i64>
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