[llvm] [AArch64] Lower for power of 2 signed divides with scalar type (PR #97879)

[via llvm-commits]

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@@ -383,4 +383,19 @@ define void @sdiv_v32i64(ptr %a) vscale_range(16,0) #0 {
   ret void
 }
 
+define i32 @sdiv_int(i32 %begin, i32 %first) #0 {
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vfdff wrote:

hi @david-arm the issue exist only iff there is option **-msve-vector-bits=256** in the command line, but it doesn't have that option in test **llvm/test/CodeGen/AArch64/sdivpow2.ll**, so would it be better to add a new separate test file ?

https://github.com/llvm/llvm-project/pull/97879