[llvm] 74984de - [X86][CodeGen] Convert masked.load/store to CLOAD/CSTORE node only when vector size = 1
Shengchen Kan via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 4 23:36:03 PDT 2024
Author: Shengchen Kan
Date: 2024-07-05T14:35:42+08:00
New Revision: 74984dee51307779a3eab10a8cd6102be37e1081
URL: https://github.com/llvm/llvm-project/commit/74984dee51307779a3eab10a8cd6102be37e1081
DIFF: https://github.com/llvm/llvm-project/commit/74984dee51307779a3eab10a8cd6102be37e1081.diff
LOG: [X86][CodeGen] Convert masked.load/store to CLOAD/CSTORE node only when vector size = 1
This fixes the crash when building llvm-test-suite with avx512f + cf.
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/test/CodeGen/X86/apx/cf.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index cc55d53597b654..95a7dee94f3ccb 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -4798,8 +4798,11 @@ void SelectionDAGBuilder::visitMaskedStore(const CallInst &I,
const auto &TTI =
TLI.getTargetMachine().getTargetTransformInfo(*I.getFunction());
SDValue StoreNode =
- !IsCompressing && TTI.hasConditionalLoadStoreForType(
- I.getArgOperand(0)->getType()->getScalarType())
+ !IsCompressing &&
+ cast<FixedVectorType>(I.getArgOperand(0)->getType())
+ ->getNumElements() == 1 &&
+ TTI.hasConditionalLoadStoreForType(
+ I.getArgOperand(0)->getType()->getScalarType())
? TLI.visitMaskedStore(DAG, sdl, getMemoryRoot(), MMO, Ptr, Src0,
Mask)
: DAG.getMaskedStore(getMemoryRoot(), sdl, Src0, Ptr, Offset, Mask,
@@ -4984,8 +4987,10 @@ void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I, bool IsExpanding) {
// variables.
SDValue Load;
SDValue Res;
- if (!IsExpanding && TTI.hasConditionalLoadStoreForType(
- Src0Operand->getType()->getScalarType()))
+ if (!IsExpanding &&
+ cast<FixedVectorType>(Src0Operand->getType())->getNumElements() == 1 &&
+ TTI.hasConditionalLoadStoreForType(
+ Src0Operand->getType()->getScalarType()))
Res = TLI.visitMaskedLoad(DAG, sdl, InChain, MMO, Load, Ptr, Src0, Mask);
else
Res = Load =
diff --git a/llvm/test/CodeGen/X86/apx/cf.ll b/llvm/test/CodeGen/X86/apx/cf.ll
index 7db1d524ebdeb9..c71d7768834f3f 100644
--- a/llvm/test/CodeGen/X86/apx/cf.ll
+++ b/llvm/test/CodeGen/X86/apx/cf.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64 -mattr=+cf -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64 -mattr=+cf,+avx512f -verify-machineinstrs | FileCheck %s
define void @basic(i32 %a, ptr %b, ptr %p, ptr %q) {
; CHECK-LABEL: basic:
@@ -103,3 +103,24 @@ entry:
%2 = bitcast <1 x i64> %1 to i64
ret i64 %2
}
+
+define void @no_crash(ptr %p, <4 x i1> %cond1, <4 x i1> %cond2) {
+; CHECK-LABEL: no_crash:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vpslld $31, %xmm1, %xmm1
+; CHECK-NEXT: vptestmd %zmm1, %zmm1, %k0
+; CHECK-NEXT: kshiftlw $12, %k0, %k0
+; CHECK-NEXT: kshiftrw $12, %k0, %k1
+; CHECK-NEXT: vpslld $31, %xmm0, %xmm0
+; CHECK-NEXT: vptestmd %zmm0, %zmm0, %k0
+; CHECK-NEXT: kshiftlw $12, %k0, %k0
+; CHECK-NEXT: kshiftrw $12, %k0, %k2
+; CHECK-NEXT: vmovdqu64 (%rdi), %zmm0 {%k2} {z}
+; CHECK-NEXT: vmovdqu64 %zmm0, (%rdi) {%k1}
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+entry:
+ %0 = call <4 x i64> @llvm.masked.load.v4i64.p0(ptr %p, i32 8, <4 x i1> %cond1, <4 x i64> poison)
+ call void @llvm.masked.store.v4i64.p0(<4 x i64> %0, ptr %p, i32 8, <4 x i1> %cond2)
+ ret void
+}
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