[llvm] [AMDGPU] Define constrained multi-dword scalar load instructions. (PR #96161)

[Matt Arsenault via llvm-commits]

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@@ -167,6 +167,20 @@ multiclass SM_Pseudo_Loads<RegisterClass baseClass,
   def _IMM : SM_Load_Pseudo <opName, baseClass, dstClass, IMM_Offset>;
   def _SGPR : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_Offset>;
   def _SGPR_IMM : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_IMM_Offset>;
+
+  // The constrained multi-dword load equivalents with early clobber flag at
+  // the dst operand. They are needed only for codegen and there is no need for
+  // their real opcodes.
+  let SubtargetPredicate = isGFX8Plus,
+      Constraints = !if(!gt(dstClass.RegTypes[0].Size, 32),
+                         "@earlyclobber $sdst", "") in {
+    let PseudoInstr = NAME # !cast<OffsetMode>(IMM_Offset).Variant in
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arsenm wrote:

You are repeating the different addressing mode forms for ec. You have 4 statements duplicated, just with an ec suffix. You can introduce an intermediate multiclass that defines the _IMM, _SGPR, _SGPR_IMM fields, and a level down defm's that without a suffix, and with the _ec suffix. That way you only need to spell out all the addressing forms once 

https://github.com/llvm/llvm-project/pull/96161