[llvm] [BOLT][AArch64] Implemented createDummyReturnFunction. (PR #96626)

[Pavel Samolysov via llvm-commits]

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@@ -706,8 +706,20 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
     unsigned ShiftVal = AArch64_AM::getArithShiftValue(OperandExtension);
     AArch64_AM::ShiftExtendType ExtendType =
         AArch64_AM::getArithExtendType(OperandExtension);
-    if (ShiftVal != 2)
-      llvm_unreachable("Failed to match indirect branch! (fragment 2)");
+    if (ShiftVal != 2) {
+      // TODO: Handle the patten where ShiftVal != 2.
+      // The following code sequence below has no shift amount,
+      // the range could be 0 to 4.
+      // The pattern comes from libc, it occurs when the binary is static.
+      //   adr     x6, 0x219fb0 <sigall_set+0x88>
+      //   add     x6, x6, x14, lsl #2
+      //   ldr     w7, [x6]
+      //   add     x6, x6, w7, sxtw => no shift amount
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samolisov wrote:

I'm sure you are familiar with this, but I believe this should be documented somewhere. This `add` is a different kind of adds in the AArach64 architecture: *ADD (extended register)* (the documentation must be somewhere there https://developer.arm.com/documentation/ddi0602/latest/Base-Instructions/ADD--extended-register---Add--extended-register-- ) This kind of instructions also may have an [optional] shift, but the main intent is to (sign-)extend a value in `w7` (here) to 64 bits.

Personally, I see no problem just to ignore the absence of a shift amount here.

https://github.com/llvm/llvm-project/pull/96626