[llvm] [RISCV] Allow non-power-of-2 vectors for VLS code generation (PR #97010)

[Luke Lau via llvm-commits]

lukel97 wrote:

Nice! I think this will be very important to have for RISC-V's SLP.

As an alternative to creating new MVTs for odd sizes though, have you considered just letting SelectionDAG widen them to the next legal VL? Asides from reductions and loads/stores, increasing the VL shouldn't impact performance. I also landed a patch a few years ago that should widen loads and stores of illegal vector sizes to VP ops: https://reviews.llvm.org/D148713

And then to avoid VL toggles from the discrepancy between the widened ops VLs and loads/stores VLs, I think my original plan was to take advantage of https://llvm.org/devmtg/2023-05/slides/Posters/01-Albano-VectorPredictionPoster.pdf somehow to reduce the VL of the widened ops

https://github.com/llvm/llvm-project/pull/97010