[llvm] [AArch64] Add flag setting instructions to scheduling model. (PR #96880)

[Ricardo Jesus via llvm-commits]

================
@@ -1108,12 +1108,18 @@ def : InstRW<[V2Write_1cyc_1B_1R], (instrs BL, BLR)>;
 // ALU, basic
 // ALU, basic, flagset
 def : SchedAlias<WriteI, V2Write_1cyc_1I>;
-def : InstRW<[V2Write_1cyc_1F], (instregex "^(ADC|SBC)S[WX]r$")>;
+def : InstRW<[V2Write_1cyc_1F], (instregex "^(ADD|SUB)S[WX]r[ir]$",
----------------
rj-jesus wrote:

I see, perfect, thanks for clarifying.

https://github.com/llvm/llvm-project/pull/96880