[llvm] [AArch64] Add flag setting instructions to scheduling model. (PR #96880)

[David Green via llvm-commits]

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@@ -1108,12 +1108,18 @@ def : InstRW<[V2Write_1cyc_1B_1R], (instrs BL, BLR)>;
 // ALU, basic
 // ALU, basic, flagset
 def : SchedAlias<WriteI, V2Write_1cyc_1I>;
-def : InstRW<[V2Write_1cyc_1F], (instregex "^(ADC|SBC)S[WX]r$")>;
+def : InstRW<[V2Write_1cyc_1F], (instregex "^(ADD|SUB)S[WX]r[ir]$",
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davemgreen wrote:

ADDSWrr is a psuedo that is used during codegen and turned into a ADDSWrs with a zero shift. I believe it should be treated like a (cheap) ADDSWrs for scheduling.

And for ri I believe they are constants either way, so does not apply to the same "free vs expensive shifts" as in the ADDrs variants. i.e they are always "ALU, basic, flagset".

https://github.com/llvm/llvm-project/pull/96880