[llvm] [ValueTypes] Add v1 to v12 vector type support for i1, i8, i16, f16, … (PR #96481)

[Kito Cheng via llvm-commits]

kito-cheng wrote:

> Isn't the current non-power of 2 support in SLP limited to types 1 less than a power of 2? i.e. 3, 7, 15? Why do we need 1-12?

I tried to add minimal MVT for non-power-of 2 support when enable that on RISC-V, and I got crash due to lack some of MVT, and then it got stable (no crash!) until almost full set of v1 to v12 supports, give some practical example is: during the selection dag it may use v7i8/v7i1 when selecting v7i32 instruction , and it will got assertion failure due to lack of v7i8 and/or v7i1.

https://github.com/llvm/llvm-project/pull/96481