[llvm] [AMDGPU]Optimize SGPR spills (PR #93668)

[Vikash Gupta via llvm-commits]

vg0204 wrote:

> the idea is to locate the buffer_load_dword in integrator_intersect_shadow which has invalid s[0:3] in the bad case and locate the counter part in the good case. By comparing the ISA, find the def of s[0:3] or chase further to find the instruction that causes invalid def of s[0:3]. Then find the invalid transformation that causes that instruction by focusing on how each pass transform that instruction.
> 
> If the ISA of integrator_intersect_shadow is too different in the bad/good cases we can force noinline for callees of integrator_intersect_shadow in the hope of narrow down the issue in its callees. We may also consider other ways to minimize the difference between the bad/good cases, e.g. adding some counter or threshold in the newly added pass to control the number of changes it makes to pinpoint the minimal change that causes pass/fail.

Thank you Sam for this heads up!

https://github.com/llvm/llvm-project/pull/93668