[llvm] [RISCV] Mark all registers marked isConstant as reserved (PR #96002)

[Craig Topper via llvm-commits]

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@@ -104,14 +104,16 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   BitVector Reserved(getNumRegs());
   auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
 
-  // Mark any registers requested to be reserved as such
   for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
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topperc wrote:

Maybe `isRegisterReservedByUser` should be replaced by `isGPRRegisterReservedByUser`. My main point was that as the number of registers increases with new extensions, this loop gets more and more iterations, making the function slower even if the new registers don't need to be reserved.

https://github.com/llvm/llvm-project/pull/96002