[llvm] [MCA] Parameterize variant scheduling classes by explicit variable (PR #92849)

[Aiden Grossman via llvm-commits]

================
@@ -185,3 +188,49 @@ TEST_F(X86TestBase, TestInstructionRecycling) {
     ASSERT_EQ(*BV, *V) << "Value of '" << F << "' does not match";
   }
 }
+
+// Test that we do not depend upon the MCInst address for variant description
+// construction. This test creates two instructions that will use variant
+// description as they are both zeroing idioms, but write to different
+// registers. If the key used to access the variant instruction description is
+// the same between the descriptions (like the MCInst pointer), we will run into
+// an assertion failure due to the different writes.
----------------
boomanaiden154 wrote:

Yes. The variant class is still the same, which would normally cause a collision in the variant descriptor cache, but given that we're including the instruction hash (which includes operands/registers) in the key now, it will be unique, so the test will work as expected.

https://github.com/llvm/llvm-project/pull/92849