[llvm] [LoopVectorize][AArch64] Add limited support for scalable vectorisation of i1 types (PR #95920)

[Paul Walker via llvm-commits]

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@@ -3259,8 +3265,12 @@ InstructionCost AArch64TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Ty,
   // of <vscale x 1 x eltty> yet, so return an invalid cost to avoid selecting
   // it. This change will be removed when code-generation for these types is
   // sufficiently reliable.
+  // We also cannot handle loads or stores involving scalable vectors of i1.
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paulwalker-arm wrote:

Perhaps "We also only support full register predicate loads and stores."?

https://github.com/llvm/llvm-project/pull/95920