[llvm] [LLVM] Add `llvm.masked.compress` intrinsic (PR #92289)

[Lawrence Benson via llvm-commits]

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@@ -5720,6 +5737,23 @@ SDValue DAGTypeLegalizer::WidenVecRes_VP_STRIDED_LOAD(VPStridedLoadSDNode *N) {
   return Res;
 }
 
+SDValue DAGTypeLegalizer::WidenVecRes_MASKED_COMPRESS(SDNode *N) {
+  SDValue Vec = N->getOperand(0);
+  SDValue Mask = N->getOperand(1);
+  SDValue Passthru = N->getOperand(2);
+  EVT WideVecVT =
+      TLI.getTypeToTransformTo(*DAG.getContext(), Vec.getValueType());
+  EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(),
+                                    Mask.getValueType().getVectorElementType(),
+                                    WideVecVT.getVectorNumElements());
+
+  SDValue WideVec = ModifyToType(Vec, WideVecVT);
+  SDValue WideMask = ModifyToType(Mask, WideMaskVT);
----------------
lawben wrote:

In my understanding, we don't. If we have a `<3 x i32>` but need a `<4 x i32>`, the "new" fourth element is only relevant for the register but not to the user. The fourth `Vec` and `Passthru` values are both `undef`, so it does not really matter if the mask selects them or not. Please correct me if I'm wrong.

https://github.com/llvm/llvm-project/pull/92289