[llvm] cba4dfd - [RegAllocFast] Use unsigned for operand indices
Alexis Engelke via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 21 03:26:04 PDT 2024
Author: Alexis Engelke
Date: 2024-06-21T10:25:28Z
New Revision: cba4dfdd2fd0515821459b50947f4ec0d8b5c58a
URL: https://github.com/llvm/llvm-project/commit/cba4dfdd2fd0515821459b50947f4ec0d8b5c58a
DIFF: https://github.com/llvm/llvm-project/commit/cba4dfdd2fd0515821459b50947f4ec0d8b5c58a.diff
LOG: [RegAllocFast] Use unsigned for operand indices
MachineInstr operand indices can be up 24 bits currently. Use unsigned
as consistent data type for operand indices instead of uint16_t.
Added:
Modified:
llvm/lib/CodeGen/RegAllocFast.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp
index 09ce8c42a3850..d936147107c57 100644
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -258,7 +258,7 @@ class RegAllocFastImpl {
/// cannot be allocated.
RegUnitSet UsedInInstr;
RegUnitSet PhysRegUses;
- SmallVector<uint16_t, 8> DefOperandIndexes;
+ SmallVector<unsigned, 8> DefOperandIndexes;
// Register masks attached to the current instruction.
SmallVector<const uint32_t *> RegMasks;
@@ -1314,7 +1314,7 @@ void RegAllocFastImpl::findAndSortDefOperandIndexes(const MachineInstr &MI) {
}
}
- llvm::sort(DefOperandIndexes, [&](uint16_t I0, uint16_t I1) {
+ llvm::sort(DefOperandIndexes, [&](unsigned I0, unsigned I1) {
const MachineOperand &MO0 = MI.getOperand(I0);
const MachineOperand &MO1 = MI.getOperand(I1);
Register Reg0 = MO0.getReg();
@@ -1439,7 +1439,7 @@ void RegAllocFastImpl::allocateInstruction(MachineInstr &MI) {
while (ReArrangedImplicitOps) {
ReArrangedImplicitOps = false;
findAndSortDefOperandIndexes(MI);
- for (uint16_t OpIdx : DefOperandIndexes) {
+ for (unsigned OpIdx : DefOperandIndexes) {
MachineOperand &MO = MI.getOperand(OpIdx);
LLVM_DEBUG(dbgs() << "Allocating " << MO << '\n');
Register Reg = MO.getReg();
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