[llvm] [AMDGPU] In instruction selector, allow copy from physical reg to s1 (PR #96157)

[Matt Arsenault via llvm-commits]

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@@ -131,6 +131,16 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
   Register SrcReg = Src.getReg();
 
   if (isVCC(DstReg, *MRI)) {
+    // In planned update of calling convention, i1 arguments/returns are
+    // assigned to SGPRs without promoting to i32. The following if statement
+    // allows insturctions such as "%0:sreg_64_xexec(s1) = COPY $sgpr4_sgpr5"
+    // to be accepted.
+    if (SrcReg.isPhysical() && SrcReg != AMDGPU::SCC) {
+      const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(DstReg);
+      if (DstRC)
+        return DstRC->contains(SrcReg);
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arsenm wrote:

Should be covering regclass or reg bank consistently. Really the case you are looking for is isVCC on the SrcReg 

https://github.com/llvm/llvm-project/pull/96157