[llvm] [RISCV][PoC] Schedule RVV instructions with same type first (PR #95924)

[Pengcheng Wang via llvm-commits]

wangpc-pp wrote:

> > ~What do you think about the following idea:~ ~1. RISCVMachineScheduler does `RISCVMachineScheduler::pickNodeFromQueue`, and the only job is to group RVV instructions according to same vtype~ ~2. Run RISCVVSETVLIInsertion~ ~3. Run MachineScheduler, whose job is to put the instructions in a good order for register allocation, also taking into account latencies and processor resources~ ~4. Run register allocation~ ~5. If the subtarget enables PostMachineScheduler, run it.`~
> > ~This approach would keep the RISCVMachineScheduler simple, since it could ignore register pressure, latencies, and processor resource usage. By running the normal MachineScheduler after VSETVLI insertion, the hope is that we have more freedom on scheduling since less `vsetvli` instructions means less instruction dependencies, meaning more scheduler freedom. At this point, we are accounting for register pressure, latencies, and processor resources.~
> > EDIT: I forgot RISCVVSETVLIInsertion is after RA, so you can ignore this idea. You probably need to balance grouping vtypes, latencies, register pressures, and resource usage at the same time, otherwise individual pass approach will undo changes made in the first pass.
> 
> We could use mutation to constrain the same group of vtype instructions instead of the vsetvli insertion to create barriers between instructions. Based on my experience, this approach still disrupts some patterns in step 3. At best, it eliminates some vsetvli instructions; at worst, it introduces additional spills and reloads. This doesn't seem ideal.

I have thought about the mutation way before but I didn't have a try. I think that can be another feasible approach. Do you have a prototype that can be evaluated?

https://github.com/llvm/llvm-project/pull/95924