[llvm] [RISCV] Relax RISCVInsertVSETVLI output VL peeking to cover registers (PR #96200)

[Piyou Chen via llvm-commits]

BeMg wrote:

Seem LLVM :: Transforms/LoopStrengthReduce/RISCV/lsr-drop-solution.ll also need update?

https://github.com/llvm/llvm-project/pull/96200