[llvm] eea150c - [VPlan] Include IV phi and backedge cost in VPlan cost computation.
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 20 12:44:32 PDT 2024
Author: Florian Hahn
Date: 2024-06-20T20:44:17+01:00
New Revision: eea150c84053035163f307b46549a2997a343ce9
URL: https://github.com/llvm/llvm-project/commit/eea150c84053035163f307b46549a2997a343ce9
DIFF: https://github.com/llvm/llvm-project/commit/eea150c84053035163f307b46549a2997a343ce9.diff
LOG: [VPlan] Include IV phi and backedge cost in VPlan cost computation.
In WebAssembly, costs != 0 are assigned to be backedge and induction
phis, so make sure we include those costs in the VPlan-based cost model.
This fixes a downstream crash with WebAssembly after 242cc200ccb
(https://github.com/llvm/llvm-project/pull/92555)
Added:
llvm/test/Transforms/LoopVectorize/WebAssembly/induction-branch-cost.ll
llvm/test/Transforms/LoopVectorize/WebAssembly/lit.local.cfg
Modified:
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
llvm/lib/Transforms/Vectorize/VPlan.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index d4a2399f09369..63e7c55791f2d 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -7325,38 +7325,31 @@ InstructionCost LoopVectorizationPlanner::cost(VPlan &Plan,
// cost model. Note that we do this as pre-processing; the VPlan may not have
// any recipes associated with the original induction increment instruction
// and may replace truncates with VPWidenIntOrFpInductionRecipe. We precompute
- // the cost of both induction increment instructions that are represented by
- // recipes and those that are not, to avoid distinguishing between them here,
- // and skip all recipes that represent induction increments (the former case)
- // later on, if they exist, to avoid counting them twice. Similarly we
- // pre-compute the cost of any optimized truncates.
+ // the cost of induction phis and increments (both that are represented by
+ // recipes and those that are not), to avoid distinguishing between them here,
+ // and skip all recipes that represent induction phis and increments (the
+ // former case) later on, if they exist, to avoid counting them twice.
+ // Similarly we pre-compute the cost of any optimized truncates.
// TODO: Switch to more accurate costing based on VPlan.
for (const auto &[IV, IndDesc] : Legal->getInductionVars()) {
Instruction *IVInc = cast<Instruction>(
IV->getIncomingValueForBlock(OrigLoop->getLoopLatch()));
- if (CostCtx.SkipCostComputation.insert(IVInc).second) {
- InstructionCost InductionCost = CostCtx.getLegacyCost(IVInc, VF);
- LLVM_DEBUG({
- dbgs() << "Cost of " << InductionCost << " for VF " << VF
- << ":\n induction increment " << *IVInc << "\n";
- IVInc->dump();
- });
- Cost += InductionCost;
- }
+ SmallVector<Instruction *> IVInsts = {IV, IVInc};
for (User *U : IV->users()) {
auto *CI = cast<Instruction>(U);
if (!CostCtx.CM.isOptimizableIVTruncate(CI, VF))
continue;
- assert(!CostCtx.SkipCostComputation.contains(CI) &&
- "Same cast for multiple inductions?");
- CostCtx.SkipCostComputation.insert(CI);
- InstructionCost CastCost = CostCtx.getLegacyCost(CI, VF);
+ IVInsts.push_back(CI);
+ }
+ for (Instruction *IVInst : IVInsts) {
+ if (!CostCtx.SkipCostComputation.insert(IVInst).second)
+ continue;
+ InstructionCost InductionCost = CostCtx.getLegacyCost(IVInst, VF);
LLVM_DEBUG({
- dbgs() << "Cost of " << CastCost << " for VF " << VF
- << ":\n induction cast " << *CI << "\n";
- CI->dump();
+ dbgs() << "Cost of " << InductionCost << " for VF " << VF
+ << ": induction instruction " << *IVInst << "\n";
});
- Cost += CastCost;
+ Cost += InductionCost;
}
}
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.cpp b/llvm/lib/Transforms/Vectorize/VPlan.cpp
index 3ad1ae3681184..fe6de4891a213 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlan.cpp
@@ -764,6 +764,11 @@ InstructionCost VPRegionBlock::cost(ElementCount VF, VPCostContext &Ctx) {
InstructionCost Cost = 0;
for (VPBlockBase *Block : vp_depth_first_shallow(getEntry()))
Cost += Block->cost(VF, Ctx);
+ InstructionCost BackedgeCost =
+ Ctx.TTI.getCFInstrCost(Instruction::Br, TTI::TCK_RecipThroughput);
+ LLVM_DEBUG(dbgs() << "Cost of " << BackedgeCost << " for VF " << VF
+ << ": vector loop backedge\n");
+ Cost += BackedgeCost;
return Cost;
}
diff --git a/llvm/test/Transforms/LoopVectorize/WebAssembly/induction-branch-cost.ll b/llvm/test/Transforms/LoopVectorize/WebAssembly/induction-branch-cost.ll
new file mode 100644
index 0000000000000..785af1551dd28
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/WebAssembly/induction-branch-cost.ll
@@ -0,0 +1,77 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -p loop-vectorize -S %s | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-f128:64-n32:64-S128-ni:1:10:20"
+target triple = "wasm32-unknown-emscripten"
+
+define void @induction_phi_and_branch_cost(ptr %end, ptr %start.1, ptr %start.2) #0 {
+; CHECK-LABEL: define void @induction_phi_and_branch_cost(
+; CHECK-SAME: ptr [[END:%.*]], ptr [[START_1:%.*]], ptr [[START_2:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[END2:%.*]] = ptrtoint ptr [[END]] to i32
+; CHECK-NEXT: [[START_11:%.*]] = ptrtoint ptr [[START_1]] to i32
+; CHECK-NEXT: [[TMP0:%.*]] = sub i32 [[START_11]], [[END2]]
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[TMP0]], 2
+; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i32 [[TMP1]], 1
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP2]], 4
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP2]], 4
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP2]], [[N_MOD_VF]]
+; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[N_VEC]], -4
+; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START_1]], i32 [[TMP3]]
+; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[N_VEC]], -4
+; CHECK-NEXT: [[IND_END3:%.*]] = getelementptr i8, ptr [[START_2]], i32 [[TMP4]]
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i32 [[INDEX]], -4
+; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[OFFSET_IDX]], 0
+; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START_2]], i32 [[TMP5]]
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i32 0
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], i32 -3
+; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP7]], align 4
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP2]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[START_1]], %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL4:%.*]] = phi ptr [ [[IND_END3]], %[[MIDDLE_BLOCK]] ], [ [[START_2]], %[[ENTRY]] ]
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[PTR_IV_2:%.*]] = phi ptr [ [[BC_RESUME_VAL4]], %[[SCALAR_PH]] ], [ [[PTR_IV_2_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr nusw i8, ptr [[PTR_IV]], i32 -4
+; CHECK-NEXT: [[PTR_IV_2_NEXT]] = getelementptr i8, ptr [[PTR_IV_2]], i32 -4
+; CHECK-NEXT: store i32 0, ptr [[PTR_IV_2]], align 4
+; CHECK-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV]], [[END]]
+; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %ptr.iv = phi ptr [ %start.1, %entry ], [ %ptr.iv.next, %loop ]
+ %ptr.iv.2 = phi ptr [ %start.2, %entry ], [ %ptr.iv.2.next, %loop ]
+ %ptr.iv.next = getelementptr nusw i8, ptr %ptr.iv, i32 -4
+ %ptr.iv.2.next = getelementptr i8, ptr %ptr.iv.2, i32 -4
+ store i32 0, ptr %ptr.iv.2, align 4
+ %ec = icmp eq ptr %ptr.iv, %end
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+attributes #0 = { "target-features"="+simd128" }
+;.
+; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
+; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
+; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
+; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
+;.
diff --git a/llvm/test/Transforms/LoopVectorize/WebAssembly/lit.local.cfg b/llvm/test/Transforms/LoopVectorize/WebAssembly/lit.local.cfg
new file mode 100644
index 0000000000000..d5f39ab4dbc8c
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/WebAssembly/lit.local.cfg
@@ -0,0 +1,2 @@
+if not "WebAssembly" in config.root.targets:
+ config.unsupported = True
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