[llvm] [SCEV] Append disjoint flag when mapping an Or instruction (PR #96208)

[Nikita Popov via llvm-commits]

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@@ -5287,9 +5287,14 @@ static std::optional<BinaryOp> MatchBinaryOp(Value *V, const DataLayout &DL,
     return BinaryOp(Op);
 
   case Instruction::Or: {
+    auto *Op0 = Op->getOperand(0);
+    auto *Op1 = Op->getOperand(1);
+    if (haveNoCommonBitsSet(Op0, Op1, SimplifyQuery(DL, &DT, &AC, CxtI)))
+      cast<PossiblyDisjointInst>(Op)->setIsDisjoint(true);
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nikic wrote:

You can't modify IR inside SCEV.

https://github.com/llvm/llvm-project/pull/96208