[llvm] [RISCV][PoC] Schedule RVV instructions with same type first (PR #95924)

[Michael Maitland via llvm-commits]

michaelmaitland wrote:

What do you think about the following idea:
1. RISCVMachineScheduler does `RISCVMachineScheduler::pickNodeFromQueue`, and the only job is to group RVV instructions according to same vtype
2. Run RISCVVSETVLIInsertion
3. Run MachineScheduler, whose job is to put the instructions in a good order for register allocation, also taking into account latencies and processor resources
4. Run register allocation
5. If the subtarget enables PostMachineScheduler, run it.

This approach would keep the RISCVMachineScheduler simple, since it could ignore register pressure, latencies, and processor resource usage. By running the normal MachineScheduler after VSETVLI insertion, the hope is that we have more freedom on scheduling since less `vsetvli` instructions means less instruction dependencies, meaning more scheduler freedom. At this point, we are accounting for register pressure, latencies, and processor resources. 

https://github.com/llvm/llvm-project/pull/95924