[llvm] 898b8a4 - [PPC] Add DwarfRegAlias for VSRPair (#95837)

[via llvm-commits]

Author: Zaara Syeda
Date: 2024-06-20T11:30:58-04:00
New Revision: 898b8a42b5fde2738da46ec9f5b427693bc681a1

URL: https://github.com/llvm/llvm-project/commit/898b8a42b5fde2738da46ec9f5b427693bc681a1
DIFF: https://github.com/llvm/llvm-project/commit/898b8a42b5fde2738da46ec9f5b427693bc681a1.diff

LOG: [PPC] Add DwarfRegAlias for VSRPair (#95837)

Add DwarfRegAlias for VSRPair as it shares dwarfRegNum with the VR
registers.

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/PPCRegisterInfo.td
    llvm/test/CodeGen/PowerPC/ppc64-anyregcc.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
index 8a37e40414eee..fdbdc14736c86 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -199,7 +199,7 @@ let SubRegIndices = [sub_vsx0, sub_vsx1] in {
     def VSRp#!add(!srl(Index, 1), 16) :
       VSRPair<!add(!srl(Index, 1), 16), "vsp"#!add(Index, 32),
               [!cast<VR>("V"#Index), !cast<VR>("V"#!add(Index, 1))]>,
-      DwarfRegNum<[-1, -1]>;
+              DwarfRegAlias<!cast<VR>("V"#Index)>;
   }
 }
 

diff  --git a/llvm/test/CodeGen/PowerPC/ppc64-anyregcc.ll b/llvm/test/CodeGen/PowerPC/ppc64-anyregcc.ll
index 9b48fb72dc7cf..b84f2a1ee3ac1 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64-anyregcc.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-anyregcc.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mcpu=pwr10 -verify-machineinstrs < %s | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"