[llvm] [WIP][PowerPC] Add phony subregisters to cover the high half of the VSX registers. (PR #94628)

[Stefan Pintilie via llvm-commits]

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@@ -3672,6 +3672,14 @@ bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) {
     // having stale segments.
     LHSVals.pruneMainSegments(LHS, ShrinkMainRange);
 
+    LHSVals.pruneSubRegValues(LHS, ShrinkMask);
+    RHSVals.pruneSubRegValues(LHS, ShrinkMask);
+  } else if (TrackSubRegLiveness && !CP.getDstIdx() && CP.getSrcIdx()) {
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stefanp-ibm wrote:

> I'm not sure we can achieve it in short term. Grep a bit, PowerPC has the most lines of code involving `SUBREG_TO_REG` comparing to X86 and AArch64.

I agree we should be moving away from `SUBREG_TO_REG` however I also agree that for PowerPC this is more of a long term goal. For this patch we will probably have to continue like this.

https://github.com/llvm/llvm-project/pull/94628