[llvm] b6c9dcc - [X86][CodeGen] Not emit mr_ND if rr_ND is commutable
Shengchen Kan via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 20 06:10:04 PDT 2024
Author: Shengchen Kan
Date: 2024-06-20T21:09:04+08:00
New Revision: b6c9dcc9f57b870645cb44155dc5993ec551320a
URL: https://github.com/llvm/llvm-project/commit/b6c9dcc9f57b870645cb44155dc5993ec551320a
DIFF: https://github.com/llvm/llvm-project/commit/b6c9dcc9f57b870645cb44155dc5993ec551320a.diff
LOG: [X86][CodeGen] Not emit mr_ND if rr_ND is commutable
This gives us more chance to compress instruction in X86CompressEVEX.cpp
b/c mr_ND is not a candidate of instructions to be compressed while
rm_ND is.
Added:
Modified:
llvm/lib/Target/X86/X86InstrArithmetic.td
llvm/test/CodeGen/X86/apx/adc.ll
llvm/test/CodeGen/X86/apx/add.ll
llvm/test/CodeGen/X86/apx/and.ll
llvm/test/CodeGen/X86/apx/or.ll
llvm/test/CodeGen/X86/apx/xor.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td
index 552a4a3b53208..ffa8a105e2d19 100644
--- a/llvm/lib/Target/X86/X86InstrArithmetic.td
+++ b/llvm/lib/Target/X86/X86InstrArithmetic.td
@@ -756,10 +756,11 @@ multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
def 32mr : BinOpMR_MF<BaseOpc, mnemonic, Xi32, opnode>, OpSize32;
def 64mr : BinOpMR_MF<BaseOpc, mnemonic, Xi64, opnode>;
let Predicates = [HasNDD, In64BitMode] in {
- def 8mr_ND : BinOpMR_RF<BaseOpc, mnemonic, Xi8 , opnode>;
- def 16mr_ND : BinOpMR_RF<BaseOpc, mnemonic, Xi16, opnode>, PD;
- def 32mr_ND : BinOpMR_RF<BaseOpc, mnemonic, Xi32, opnode>;
- def 64mr_ND : BinOpMR_RF<BaseOpc, mnemonic, Xi64, opnode>;
+ defvar node = !if(!eq(CommutableRR, 0), opnode, null_frag);
+ def 8mr_ND : BinOpMR_RF<BaseOpc, mnemonic, Xi8 , node>;
+ def 16mr_ND : BinOpMR_RF<BaseOpc, mnemonic, Xi16, node>, PD;
+ def 32mr_ND : BinOpMR_RF<BaseOpc, mnemonic, Xi32, node>;
+ def 64mr_ND : BinOpMR_RF<BaseOpc, mnemonic, Xi64, node>;
def 8mr_NF_ND : BinOpMR_R<BaseOpc, mnemonic, Xi8>, EVEX_NF;
def 16mr_NF_ND : BinOpMR_R<BaseOpc, mnemonic, Xi16>, EVEX_NF, PD;
def 32mr_NF_ND : BinOpMR_R<BaseOpc, mnemonic, Xi32>, EVEX_NF;
@@ -944,10 +945,11 @@ multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
def 32mr : BinOpMRF_MF<BaseOpc, mnemonic, Xi32, opnode>, OpSize32;
def 64mr : BinOpMRF_MF<BaseOpc, mnemonic, Xi64, opnode>;
let Predicates = [HasNDD, In64BitMode] in {
- def 8mr_ND : BinOpMRF_RF<BaseOpc, mnemonic, Xi8 , opnode>;
- def 16mr_ND : BinOpMRF_RF<BaseOpc, mnemonic, Xi16, opnode>, PD;
- def 32mr_ND : BinOpMRF_RF<BaseOpc, mnemonic, Xi32, opnode>;
- def 64mr_ND : BinOpMRF_RF<BaseOpc, mnemonic, Xi64, opnode>;
+ defvar node = !if(!eq(CommutableRR, 0), opnode, null_frag);
+ def 8mr_ND : BinOpMRF_RF<BaseOpc, mnemonic, Xi8 , node>;
+ def 16mr_ND : BinOpMRF_RF<BaseOpc, mnemonic, Xi16, node>, PD;
+ def 32mr_ND : BinOpMRF_RF<BaseOpc, mnemonic, Xi32, node>;
+ def 64mr_ND : BinOpMRF_RF<BaseOpc, mnemonic, Xi64, node>;
}
let Predicates = [In64BitMode] in {
def 8mr_EVEX : BinOpMRF_MF<BaseOpc, mnemonic, Xi8 , null_frag>, PL;
@@ -1108,14 +1110,26 @@ let isCompare = 1 in {
// Patterns to recognize loads on the LHS of an ADC. We can't make X86adc_flag
// commutable since it has EFLAGs as an input.
-def : Pat<(X86adc_flag (loadi8 addr:$src2), GR8:$src1, EFLAGS),
- (ADC8rm GR8:$src1, addr:$src2)>;
-def : Pat<(X86adc_flag (loadi16 addr:$src2), GR16:$src1, EFLAGS),
- (ADC16rm GR16:$src1, addr:$src2)>;
-def : Pat<(X86adc_flag (loadi32 addr:$src2), GR32:$src1, EFLAGS),
- (ADC32rm GR32:$src1, addr:$src2)>;
-def : Pat<(X86adc_flag (loadi64 addr:$src2), GR64:$src1, EFLAGS),
- (ADC64rm GR64:$src1, addr:$src2)>;
+let Predicates = [NoNDD] in {
+ def : Pat<(X86adc_flag (loadi8 addr:$src2), GR8:$src1, EFLAGS),
+ (ADC8rm GR8:$src1, addr:$src2)>;
+ def : Pat<(X86adc_flag (loadi16 addr:$src2), GR16:$src1, EFLAGS),
+ (ADC16rm GR16:$src1, addr:$src2)>;
+ def : Pat<(X86adc_flag (loadi32 addr:$src2), GR32:$src1, EFLAGS),
+ (ADC32rm GR32:$src1, addr:$src2)>;
+ def : Pat<(X86adc_flag (loadi64 addr:$src2), GR64:$src1, EFLAGS),
+ (ADC64rm GR64:$src1, addr:$src2)>;
+}
+let Predicates = [HasNDD] in {
+ def : Pat<(X86adc_flag (loadi8 addr:$src2), GR8:$src1, EFLAGS),
+ (ADC8rm_ND GR8:$src1, addr:$src2)>;
+ def : Pat<(X86adc_flag (loadi16 addr:$src2), GR16:$src1, EFLAGS),
+ (ADC16rm_ND GR16:$src1, addr:$src2)>;
+ def : Pat<(X86adc_flag (loadi32 addr:$src2), GR32:$src1, EFLAGS),
+ (ADC32rm_ND GR32:$src1, addr:$src2)>;
+ def : Pat<(X86adc_flag (loadi64 addr:$src2), GR64:$src1, EFLAGS),
+ (ADC64rm_ND GR64:$src1, addr:$src2)>;
+}
// Patterns to recognize RMW ADC with loads in operand 1.
def : Pat<(store (X86adc_flag GR8:$src, (loadi8 addr:$dst), EFLAGS),
diff --git a/llvm/test/CodeGen/X86/apx/adc.ll b/llvm/test/CodeGen/X86/apx/adc.ll
index 621784f86bded..f6792ad8d227b 100644
--- a/llvm/test/CodeGen/X86/apx/adc.ll
+++ b/llvm/test/CodeGen/X86/apx/adc.ll
@@ -211,7 +211,7 @@ define i8 @adc8mr(i8 %a, ptr %ptr, i8 %x, i8 %y) nounwind {
; CHECK-LABEL: adc8mr:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpb %dl, %cl # encoding: [0x38,0xd1]
-; CHECK-NEXT: adcb %dil, (%rsi), %al # encoding: [0x62,0xf4,0x7c,0x18,0x10,0x3e]
+; CHECK-NEXT: adcb (%rsi), %dil, %al # encoding: [0x62,0xf4,0x7c,0x18,0x12,0x3e]
; CHECK-NEXT: retq # encoding: [0xc3]
%b = load i8, ptr %ptr
%s = add i8 %b, %a
@@ -225,7 +225,7 @@ define i16 @adc16mr(i16 %a, ptr %ptr, i16 %x, i16 %y) nounwind {
; CHECK-LABEL: adc16mr:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpw %dx, %cx # encoding: [0x66,0x39,0xd1]
-; CHECK-NEXT: adcw %di, (%rsi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x11,0x3e]
+; CHECK-NEXT: adcw (%rsi), %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x13,0x3e]
; CHECK-NEXT: retq # encoding: [0xc3]
%b = load i16, ptr %ptr
%s = add i16 %b, %a
@@ -239,7 +239,7 @@ define i32 @adc32mr(i32 %a, ptr %ptr, i32 %x, i32 %y) nounwind {
; CHECK-LABEL: adc32mr:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpl %edx, %ecx # encoding: [0x39,0xd1]
-; CHECK-NEXT: adcl %edi, (%rsi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x11,0x3e]
+; CHECK-NEXT: adcl (%rsi), %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x13,0x3e]
; CHECK-NEXT: retq # encoding: [0xc3]
%b = load i32, ptr %ptr
%s = add i32 %b, %a
@@ -253,7 +253,7 @@ define i64 @adc64mr(i64 %a, ptr %ptr, i64 %x, i64 %y) nounwind {
; CHECK-LABEL: adc64mr:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpq %rdx, %rcx # encoding: [0x48,0x39,0xd1]
-; CHECK-NEXT: adcq %rdi, (%rsi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x11,0x3e]
+; CHECK-NEXT: adcq (%rsi), %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x13,0x3e]
; CHECK-NEXT: retq # encoding: [0xc3]
%b = load i64, ptr %ptr
%s = add i64 %b, %a
diff --git a/llvm/test/CodeGen/X86/apx/add.ll b/llvm/test/CodeGen/X86/apx/add.ll
index 7779ae599f200..334ceb2e6d76f 100644
--- a/llvm/test/CodeGen/X86/apx/add.ll
+++ b/llvm/test/CodeGen/X86/apx/add.ll
@@ -246,12 +246,12 @@ entry:
define i8 @add8mr(ptr %a, i8 noundef %b) {
; CHECK-LABEL: add8mr:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addb %sil, (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0x00,0x37]
+; CHECK-NEXT: addb (%rdi), %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0x02,0x37]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: add8mr:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} addb %sil, (%rdi), %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x00,0x37]
+; NF-NEXT: {nf} addb (%rdi), %sil, %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x02,0x37]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%t= load i8, ptr %a
@@ -262,12 +262,12 @@ entry:
define i16 @add16mr(ptr %a, i16 noundef %b) {
; CHECK-LABEL: add16mr:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addw %si, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x01,0x37]
+; CHECK-NEXT: addw (%rdi), %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x03,0x37]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: add16mr:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} addw %si, (%rdi), %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0x01,0x37]
+; NF-NEXT: {nf} addw (%rdi), %si, %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0x03,0x37]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%t= load i16, ptr %a
@@ -278,12 +278,12 @@ entry:
define i32 @add32mr(ptr %a, i32 noundef %b) {
; CHECK-LABEL: add32mr:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addl %esi, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x01,0x37]
+; CHECK-NEXT: addl (%rdi), %esi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x03,0x37]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: add32mr:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} addl %esi, (%rdi), %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x01,0x37]
+; NF-NEXT: {nf} addl (%rdi), %esi, %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x03,0x37]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%t= load i32, ptr %a
@@ -294,12 +294,12 @@ entry:
define i64 @add64mr(ptr %a, i64 noundef %b) {
; CHECK-LABEL: add64mr:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addq %rsi, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x01,0x37]
+; CHECK-NEXT: addq (%rdi), %rsi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x03,0x37]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: add64mr:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} addq %rsi, (%rdi), %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0x01,0x37]
+; NF-NEXT: {nf} addq (%rdi), %rsi, %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0x03,0x37]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%t= load i64, ptr %a
diff --git a/llvm/test/CodeGen/X86/apx/and.ll b/llvm/test/CodeGen/X86/apx/and.ll
index 58f54fbe50a52..d902f41284e33 100644
--- a/llvm/test/CodeGen/X86/apx/and.ll
+++ b/llvm/test/CodeGen/X86/apx/and.ll
@@ -248,12 +248,12 @@ entry:
define i8 @and8mr(ptr %a, i8 noundef %b) {
; CHECK-LABEL: and8mr:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andb %sil, (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0x20,0x37]
+; CHECK-NEXT: andb (%rdi), %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0x22,0x37]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: and8mr:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} andb %sil, (%rdi), %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x20,0x37]
+; NF-NEXT: {nf} andb (%rdi), %sil, %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x22,0x37]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%t= load i8, ptr %a
@@ -264,12 +264,12 @@ entry:
define i16 @and16mr(ptr %a, i16 noundef %b) {
; CHECK-LABEL: and16mr:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andw %si, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x21,0x37]
+; CHECK-NEXT: andw (%rdi), %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x23,0x37]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: and16mr:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} andw %si, (%rdi), %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0x21,0x37]
+; NF-NEXT: {nf} andw (%rdi), %si, %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0x23,0x37]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%t= load i16, ptr %a
@@ -280,12 +280,12 @@ entry:
define i32 @and32mr(ptr %a, i32 noundef %b) {
; CHECK-LABEL: and32mr:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andl %esi, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x21,0x37]
+; CHECK-NEXT: andl (%rdi), %esi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x23,0x37]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: and32mr:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} andl %esi, (%rdi), %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x21,0x37]
+; NF-NEXT: {nf} andl (%rdi), %esi, %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x23,0x37]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%t= load i32, ptr %a
@@ -296,12 +296,12 @@ entry:
define i64 @and64mr(ptr %a, i64 noundef %b) {
; CHECK-LABEL: and64mr:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andq %rsi, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x21,0x37]
+; CHECK-NEXT: andq (%rdi), %rsi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x23,0x37]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: and64mr:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} andq %rsi, (%rdi), %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0x21,0x37]
+; NF-NEXT: {nf} andq (%rdi), %rsi, %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0x23,0x37]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%t= load i64, ptr %a
diff --git a/llvm/test/CodeGen/X86/apx/or.ll b/llvm/test/CodeGen/X86/apx/or.ll
index d404279e14f7a..f7aa400714dc3 100644
--- a/llvm/test/CodeGen/X86/apx/or.ll
+++ b/llvm/test/CodeGen/X86/apx/or.ll
@@ -248,12 +248,12 @@ entry:
define i8 @or8mr(ptr %a, i8 noundef %b) {
; CHECK-LABEL: or8mr:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: orb %sil, (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0x08,0x37]
+; CHECK-NEXT: orb (%rdi), %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0x0a,0x37]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: or8mr:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} orb %sil, (%rdi), %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x08,0x37]
+; NF-NEXT: {nf} orb (%rdi), %sil, %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x0a,0x37]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%t= load i8, ptr %a
@@ -264,12 +264,12 @@ entry:
define i16 @or16mr(ptr %a, i16 noundef %b) {
; CHECK-LABEL: or16mr:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: orw %si, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x09,0x37]
+; CHECK-NEXT: orw (%rdi), %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x0b,0x37]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: or16mr:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} orw %si, (%rdi), %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0x09,0x37]
+; NF-NEXT: {nf} orw (%rdi), %si, %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0x0b,0x37]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%t= load i16, ptr %a
@@ -280,12 +280,12 @@ entry:
define i32 @or32mr(ptr %a, i32 noundef %b) {
; CHECK-LABEL: or32mr:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: orl %esi, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x09,0x37]
+; CHECK-NEXT: orl (%rdi), %esi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x0b,0x37]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: or32mr:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} orl %esi, (%rdi), %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x09,0x37]
+; NF-NEXT: {nf} orl (%rdi), %esi, %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x0b,0x37]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%t= load i32, ptr %a
@@ -296,12 +296,12 @@ entry:
define i64 @or64mr(ptr %a, i64 noundef %b) {
; CHECK-LABEL: or64mr:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: orq %rsi, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x09,0x37]
+; CHECK-NEXT: orq (%rdi), %rsi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x0b,0x37]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: or64mr:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} orq %rsi, (%rdi), %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0x09,0x37]
+; NF-NEXT: {nf} orq (%rdi), %rsi, %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0x0b,0x37]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%t= load i64, ptr %a
diff --git a/llvm/test/CodeGen/X86/apx/xor.ll b/llvm/test/CodeGen/X86/apx/xor.ll
index 436b16b4292df..6a6b699a922db 100644
--- a/llvm/test/CodeGen/X86/apx/xor.ll
+++ b/llvm/test/CodeGen/X86/apx/xor.ll
@@ -248,12 +248,12 @@ entry:
define i8 @xor8mr(ptr %a, i8 noundef %b) {
; CHECK-LABEL: xor8mr:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xorb %sil, (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0x30,0x37]
+; CHECK-NEXT: xorb (%rdi), %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0x32,0x37]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: xor8mr:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} xorb %sil, (%rdi), %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x30,0x37]
+; NF-NEXT: {nf} xorb (%rdi), %sil, %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x32,0x37]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%t= load i8, ptr %a
@@ -264,12 +264,12 @@ entry:
define i16 @xor16mr(ptr %a, i16 noundef %b) {
; CHECK-LABEL: xor16mr:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xorw %si, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x31,0x37]
+; CHECK-NEXT: xorw (%rdi), %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x33,0x37]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: xor16mr:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} xorw %si, (%rdi), %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0x31,0x37]
+; NF-NEXT: {nf} xorw (%rdi), %si, %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0x33,0x37]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%t= load i16, ptr %a
@@ -280,12 +280,12 @@ entry:
define i32 @xor32mr(ptr %a, i32 noundef %b) {
; CHECK-LABEL: xor32mr:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xorl %esi, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x31,0x37]
+; CHECK-NEXT: xorl (%rdi), %esi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x33,0x37]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: xor32mr:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} xorl %esi, (%rdi), %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x31,0x37]
+; NF-NEXT: {nf} xorl (%rdi), %esi, %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x33,0x37]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%t= load i32, ptr %a
@@ -296,12 +296,12 @@ entry:
define i64 @xor64mr(ptr %a, i64 noundef %b) {
; CHECK-LABEL: xor64mr:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xorq %rsi, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x31,0x37]
+; CHECK-NEXT: xorq (%rdi), %rsi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x33,0x37]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: xor64mr:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} xorq %rsi, (%rdi), %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0x31,0x37]
+; NF-NEXT: {nf} xorq (%rdi), %rsi, %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0x33,0x37]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%t= load i64, ptr %a
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