[llvm] [AMDGPU] New intrinsic llvm.amdgcn.pops.exiting.wave.id (PR #89612)

[Jay Foad via llvm-commits]

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@@ -1865,6 +1870,12 @@ let SubtargetPredicate = isNotGFX9Plus in {
 def : GetFPModePat<fpmode_mask_gfx6plus>;
 }
 
+let SubtargetPredicate = isGFX9GFX10 in
+def : GCNPat<
+  (int_amdgcn_pops_exiting_wave_id),
+  (S_MOV_B32_sideeffects (i32 SRC_POPS_EXITING_WAVE_ID))
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jayfoad wrote:

> > Then what would stop the MachineInstr getting CSEd, hoisted out of loops, rematerialized etc? We definitely need to prevent it from being moved past control flow so that you can write loops that poll the value.
>
> The use of reserved physical register

That does not seem to work. See: https://github.com/llvm/llvm-project/blob/af82e63c28f67bf61a9b2b0e64bc55be4acf520e/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll#L39 where `%1:sreg_32 = S_MOV_B32 $src_pops_exiting_wave_id` is hoisted by early-machinelicm.

https://github.com/llvm/llvm-project/pull/89612