[llvm] Fix unassigned add handling in aarch64 (PR #86636)

[Simon Pilgrim via llvm-commits]

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@@ -5279,6 +5279,13 @@ SDValue DAGCombiner::visitAVG(SDNode *N) {
           DAG.getNode(ISD::ADD, DL, VT, N0, DAG.getAllOnesConstant(DL, VT)));
   }
 
+  // Fold shadd(x,y) -> uhadd(x,y) if both x and y are non-negative
+  if (Opcode == ISD::SHADD && !hasOperation(ISD::SHADD, VT) &&
+      (!LegalOperations || hasOperation(ISD::UHADD, VT))) {
+    if (DAG.isKnownNeverNegative(N0) && DAG.isKnownNeverNegative(N1))
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RKSimon wrote:

DAG.SignBitIsZero 

https://github.com/llvm/llvm-project/pull/86636