[llvm] [AMDGPU] Define constrained multi-dword scalar load instructions. (PR #96161)

[Christudasan Devadasan via llvm-commits]

https://github.com/cdevadas created https://github.com/llvm/llvm-project/pull/96161

None

>From 37495cbd2f8661bddcb1cf5b7f30d1cc47297766 Mon Sep 17 00:00:00 2001
From: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
Date: Thu, 20 Jun 2024 10:00:59 +0000
Subject: [PATCH] [AMDGPU] Define constrained multi-dword scalar load
 instructions.

---
 llvm/lib/Target/AMDGPU/SMInstructions.td | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
index df1722b1f7fb4..4551a3a615b15 100644
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -167,6 +167,20 @@ multiclass SM_Pseudo_Loads<RegisterClass baseClass,
   def _IMM : SM_Load_Pseudo <opName, baseClass, dstClass, IMM_Offset>;
   def _SGPR : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_Offset>;
   def _SGPR_IMM : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_IMM_Offset>;
+
+  // The constrained multi-dword load equivalents with early clobber flag at
+  // the dst operand. They are needed only for codegen and there is no need for
+  // their real opcodes.
+  let SubtargetPredicate = isGFX8Plus,
+      Constraints = !if(!gt(dstClass.RegTypes[0].Size, 32),
+                         "@earlyclobber $sdst", "") in {
+    let PseudoInstr = NAME # !cast<OffsetMode>(IMM_Offset).Variant in
+      def _IMM_ec : SM_Load_Pseudo <opName, baseClass, dstClass, IMM_Offset>;
+    let PseudoInstr = NAME # !cast<OffsetMode>(SGPR_Offset).Variant in
+      def _SGPR_ec : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_Offset>;
+    let PseudoInstr = NAME # !cast<OffsetMode>(SGPR_IMM_Offset).Variant in
+      def _SGPR_IMM_ec : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_IMM_Offset>;
+  }
 }
 
 multiclass SM_Pseudo_Stores<RegisterClass baseClass,