[llvm] [RISCV][PoC] Schedule RVV instructions with same type first (PR #95924)

[Piyou Chen via llvm-commits]

BeMg wrote:

Except the latency and instruction count, the register pressure also need to be concerned. IIRC `GenericScheduler::tryCandidate` should responsible for it. 



https://github.com/llvm/llvm-project/pull/95924