[llvm] [StackMaps] Check both subregs and superregs for getDwarfRegNum (PR #95837)

[Zaara Syeda via llvm-commits]

https://github.com/syzaara updated https://github.com/llvm/llvm-project/pull/95837

>From 35667789a4ca64173b0240a37a8e85c1a426c2e9 Mon Sep 17 00:00:00 2001
From: Zaara Syeda <syzaara at cpap8104.rtp.raleigh.ibm.com>
Date: Mon, 17 Jun 2024 15:16:01 -0400
Subject: [PATCH 1/2] [StackMaps] Check both subregs and superregs for
 getDwarfRegNum

In getDwarfRegNum we currently only check the super-register chain until we hit
a valid dwarf register number. Registers may also share dwarf register number
with their subregs. For example with Power10, the VSRPair registers share
dwarf register number with the VR subregs.
---
 llvm/lib/CodeGen/StackMaps.cpp              | 10 +++++++++-
 llvm/lib/Target/PowerPC/PPCRegisterInfo.td  |  2 +-
 llvm/test/CodeGen/PowerPC/ppc64-anyregcc.ll |  2 +-
 3 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/CodeGen/StackMaps.cpp b/llvm/lib/CodeGen/StackMaps.cpp
index 90aa93e442cf3..1f33fd3c09994 100644
--- a/llvm/lib/CodeGen/StackMaps.cpp
+++ b/llvm/lib/CodeGen/StackMaps.cpp
@@ -191,7 +191,8 @@ unsigned StackMaps::getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx) {
   return CurIdx;
 }
 
-/// Go up the super-register chain until we hit a valid dwarf register number.
+/// Go up the super-register and sub-register chain until we hit a valid dwarf
+/// register number.
 static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) {
   int RegNum;
   for (MCPhysReg SR : TRI->superregs_inclusive(Reg)) {
@@ -199,6 +200,13 @@ static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) {
     if (RegNum >= 0)
       break;
   }
+  if (RegNum < 0) {
+    for (MCPhysReg SR : TRI->subregs_inclusive(Reg)) {
+      RegNum = TRI->getDwarfRegNum(SR, false);
+      if (RegNum >= 0)
+        break;
+    }
+  }
 
   assert(RegNum >= 0 && isUInt<16>(RegNum) && "Invalid Dwarf register number.");
   return (unsigned)RegNum;
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
index 8a37e40414eee..fdbdc14736c86 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -199,7 +199,7 @@ let SubRegIndices = [sub_vsx0, sub_vsx1] in {
     def VSRp#!add(!srl(Index, 1), 16) :
       VSRPair<!add(!srl(Index, 1), 16), "vsp"#!add(Index, 32),
               [!cast<VR>("V"#Index), !cast<VR>("V"#!add(Index, 1))]>,
-      DwarfRegNum<[-1, -1]>;
+              DwarfRegAlias<!cast<VR>("V"#Index)>;
   }
 }
 
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-anyregcc.ll b/llvm/test/CodeGen/PowerPC/ppc64-anyregcc.ll
index 9b48fb72dc7cf..4bf222e898488 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64-anyregcc.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-anyregcc.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mcpu=pwr10 -verify-machineinstrs < %s | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 

>From 66a2be5eaf175f4ea41e94f3b80a3669903039e3 Mon Sep 17 00:00:00 2001
From: Zaara Syeda <syzaara at cpap8104.rtp.raleigh.ibm.com>
Date: Wed, 19 Jun 2024 16:32:04 -0400
Subject: [PATCH 2/2] Address review comments

---
 llvm/lib/CodeGen/StackMaps.cpp              | 10 +---------
 llvm/test/CodeGen/PowerPC/ppc64-anyregcc.ll |  1 +
 2 files changed, 2 insertions(+), 9 deletions(-)

diff --git a/llvm/lib/CodeGen/StackMaps.cpp b/llvm/lib/CodeGen/StackMaps.cpp
index 1f33fd3c09994..90aa93e442cf3 100644
--- a/llvm/lib/CodeGen/StackMaps.cpp
+++ b/llvm/lib/CodeGen/StackMaps.cpp
@@ -191,8 +191,7 @@ unsigned StackMaps::getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx) {
   return CurIdx;
 }
 
-/// Go up the super-register and sub-register chain until we hit a valid dwarf
-/// register number.
+/// Go up the super-register chain until we hit a valid dwarf register number.
 static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) {
   int RegNum;
   for (MCPhysReg SR : TRI->superregs_inclusive(Reg)) {
@@ -200,13 +199,6 @@ static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) {
     if (RegNum >= 0)
       break;
   }
-  if (RegNum < 0) {
-    for (MCPhysReg SR : TRI->subregs_inclusive(Reg)) {
-      RegNum = TRI->getDwarfRegNum(SR, false);
-      if (RegNum >= 0)
-        break;
-    }
-  }
 
   assert(RegNum >= 0 && isUInt<16>(RegNum) && "Invalid Dwarf register number.");
   return (unsigned)RegNum;
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-anyregcc.ll b/llvm/test/CodeGen/PowerPC/ppc64-anyregcc.ll
index 4bf222e898488..b84f2a1ee3ac1 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64-anyregcc.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-anyregcc.ll
@@ -1,3 +1,4 @@
+; RUN: llc -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mcpu=pwr10 -verify-machineinstrs < %s | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"