[llvm] [PPC]Optimize zeroing accumulator and spilling instructions into simple instructions (PR #96094)
zhijian lin via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 19 10:25:25 PDT 2024
https://github.com/diggerlin created https://github.com/llvm/llvm-project/pull/96094
in the patch , it will optimize the following instructions
```
xxsetaccz 0
xxmfacc 0
stxv 0, 1792(1)
stxv 1, 1776(1)
stxv 2, 1760(1)
stxv 3, 1744(1)
```
to
```
xxlxor 0, 0, 0
stxv 0, 1792(1)
stxv 0, 1776(1)
stxv 0, 1760(1)
stxv 0, 1744(1)
```
>From 26beee4aa0a87575db1946998739e0b3203f394b Mon Sep 17 00:00:00 2001
From: zhijian <zhijian at ca.ibm.com>
Date: Tue, 18 Jun 2024 16:08:49 -0400
Subject: [PATCH] first commit of replace XXSETACCZ
---
.../lib/Target/PowerPC/PPCPreEmitPeephole.cpp | 88 +++++++++++++++++++
llvm/test/CodeGen/PowerPC/mma-intrinsics.ll | 36 ++++----
2 files changed, 104 insertions(+), 20 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
index d45edd74ab854..4dac9d1708d8a 100644
--- a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
@@ -109,6 +109,93 @@ static bool hasPCRelativeForm(MachineInstr &Use) {
MachineFunctionProperties::Property::NoVRegs);
}
+ // The funtion will simply the zeroing accumulator and spilling instrcutions
+ // into simple xxlxor and spilling instrcuctions.
+ // From:
+ // setaccz acci
+ // xxmfacc acci
+ // stxv vsr(i*4+0), D(1)
+ // stxv vsr(i*4+1), D-16(1)
+ // stxv vsr(i*4+2), D-32(1)
+ // stxv vsr(i*4+3), D-48(1)
+
+ // To:
+ // xxlxor vsr(i*4), 0, 0
+ // stxv vsr(i*4), D(1)
+ // stxv vsr(i*4), D-16(1)
+ // stxv vsr(i*4), D-32(1)
+ // stxv vsr(i*4), D-48(1)
+ bool
+ OptimizeZeroingAccumulatorSpilling(MachineBasicBlock &MBB,
+ const TargetRegisterInfo *TRI) const {
+ bool changed = false;
+ for (auto BBI = MBB.instr_begin(); BBI != MBB.instr_end(); ++BBI) {
+ if (BBI->getOpcode() != PPC::XXSETACCZ)
+ continue;
+
+ Register ACCZReg = BBI->getOperand(0).getReg();
+
+ DenseSet<MachineInstr *> InstrsToErase;
+ InstrsToErase.insert(&*BBI++);
+
+ if (BBI->getOpcode() != PPC::XXMFACC) {
+ --BBI;
+ continue;
+ }
+
+ Register ACCWReg = BBI->getOperand(0).getReg();
+
+ if (ACCWReg != ACCZReg)
+ continue;
+
+ auto XXMFACCInstr = BBI;
+ InstrsToErase.insert(&*BBI++);
+
+ Register VSLRegBase = (ACCWReg - PPC::ACC0) * 4 + PPC::VSL0;
+ bool isVSLRegBaseKilled = false;
+ for (unsigned InstrCount = 0; InstrCount < 4; ++InstrCount, ++BBI) {
+ if (BBI->getOpcode() == PPC::STXV) {
+ Register Reg0 = BBI->getOperand(0).getReg();
+ // If the VSLRegBase Register is killed, we put the kill in the
+ // last STXV instruction.
+ if (Reg0 == VSLRegBase && BBI->getOperand(0).isKill())
+ isVSLRegBaseKilled = true;
+ if (Reg0 < VSLRegBase || Reg0 > VSLRegBase + 3)
+ continue;
+ } else {
+ --BBI;
+ continue;
+ }
+ }
+
+ BBI = XXMFACCInstr;
+ BBI++;
+ for (unsigned InstrCount = 0; InstrCount < 4; ++InstrCount, ++BBI) {
+ Register VSLiReg = BBI->getOperand(0).getReg();
+ BBI->substituteRegister(VSLiReg, VSLRegBase, 0, *TRI);
+ BBI->getOperand(0).setIsKill(false);
+ }
+
+ if (isVSLRegBaseKilled)
+ (--BBI)->getOperand(0).setIsKill(true);
+
+ DebugLoc DL = XXMFACCInstr->getDebugLoc();
+ const PPCInstrInfo *TII = XXMFACCInstr->getMF()
+ ->getSubtarget<PPCSubtarget>()
+ .getInstrInfo();
+
+ BuildMI(MBB, &*XXMFACCInstr, DL, TII->get(PPC::XXLXOR), VSLRegBase)
+ .addReg(VSLRegBase,RegState::Undef)
+ .addReg(VSLRegBase,RegState::Undef);
+
+ for (MachineInstr *MI : InstrsToErase)
+ MI->eraseFromParent();
+
+ changed |= true;
+ }
+ return changed;
+ }
+
// This function removes any redundant load immediates. It has two level
// loops - The outer loop finds the load immediates BBI that could be used
// to replace following redundancy. The inner loop scans instructions that
@@ -466,6 +553,7 @@ static bool hasPCRelativeForm(MachineInstr &Use) {
Changed |= removeRedundantLIs(MBB, TRI);
Changed |= addLinkerOpt(MBB, TRI);
Changed |= removeAccPrimeUnprime(MBB);
+ Changed |= OptimizeZeroingAccumulatorSpilling(MBB, TRI);
for (MachineInstr &MI : MBB) {
unsigned Opc = MI.getOpcode();
if (Opc == PPC::UNENCODED_NOP) {
diff --git a/llvm/test/CodeGen/PowerPC/mma-intrinsics.ll b/llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
index 53b0a2737122e..17e24eefc2580 100644
--- a/llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
+++ b/llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
@@ -115,22 +115,20 @@ declare <512 x i1> @llvm.ppc.mma.xxsetaccz()
define void @int_xxsetaccz(ptr %ptr) {
; CHECK-LABEL: int_xxsetaccz:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxsetaccz acc0
-; CHECK-NEXT: xxmfacc acc0
+; CHECK-NEXT: xxlxor vs0, vs0, vs0
; CHECK-NEXT: stxv vs0, 48(r3)
-; CHECK-NEXT: stxv vs1, 32(r3)
-; CHECK-NEXT: stxv vs2, 16(r3)
-; CHECK-NEXT: stxv vs3, 0(r3)
+; CHECK-NEXT: stxv vs0, 32(r3)
+; CHECK-NEXT: stxv vs0, 16(r3)
+; CHECK-NEXT: stxv vs0, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: int_xxsetaccz:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: xxsetaccz acc0
-; CHECK-BE-NEXT: xxmfacc acc0
-; CHECK-BE-NEXT: stxv vs1, 16(r3)
+; CHECK-BE-NEXT: xxlxor vs0, vs0, vs0
+; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3)
-; CHECK-BE-NEXT: stxv vs3, 48(r3)
-; CHECK-BE-NEXT: stxv vs2, 32(r3)
+; CHECK-BE-NEXT: stxv vs0, 48(r3)
+; CHECK-BE-NEXT: stxv vs0, 32(r3)
; CHECK-BE-NEXT: blr
entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()
@@ -143,22 +141,20 @@ declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble
define void @disass_acc(ptr %ptr1, ptr %ptr2, ptr %ptr3, ptr %ptr4) {
; CHECK-LABEL: disass_acc:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxsetaccz acc0
-; CHECK-NEXT: xxmfacc acc0
-; CHECK-NEXT: stxv vs3, 0(r3)
-; CHECK-NEXT: stxv vs2, 0(r4)
-; CHECK-NEXT: stxv vs1, 0(r5)
+; CHECK-NEXT: xxlxor vs0, vs0, vs0
+; CHECK-NEXT: stxv vs0, 0(r3)
+; CHECK-NEXT: stxv vs0, 0(r4)
+; CHECK-NEXT: stxv vs0, 0(r5)
; CHECK-NEXT: stxv vs0, 0(r6)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: disass_acc:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: xxsetaccz acc0
-; CHECK-BE-NEXT: xxmfacc acc0
+; CHECK-BE-NEXT: xxlxor vs0, vs0, vs0
; CHECK-BE-NEXT: stxv vs0, 0(r3)
-; CHECK-BE-NEXT: stxv vs1, 0(r4)
-; CHECK-BE-NEXT: stxv vs2, 0(r5)
-; CHECK-BE-NEXT: stxv vs3, 0(r6)
+; CHECK-BE-NEXT: stxv vs0, 0(r4)
+; CHECK-BE-NEXT: stxv vs0, 0(r5)
+; CHECK-BE-NEXT: stxv vs0, 0(r6)
; CHECK-BE-NEXT: blr
entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()
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