[llvm] 2a57a08 - [PowerPC] Regenerate p8altivec-shuffles-pred.ll with update_llc_test_checks script

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2024-06-19T16:55:33+01:00
New Revision: 2a57a08829e8079b59c95ad14f71a1417006c9b5

URL: https://github.com/llvm/llvm-project/commit/2a57a08829e8079b59c95ad14f71a1417006c9b5
DIFF: https://github.com/llvm/llvm-project/commit/2a57a08829e8079b59c95ad14f71a1417006c9b5.diff

LOG: [PowerPC] Regenerate p8altivec-shuffles-pred.ll with update_llc_test_checks script

Added: 
    

Modified: 
    llvm/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll b/llvm/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll
index c8cad4bf184f8..3ec4a226e0dac 100644
--- a/llvm/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll
+++ b/llvm/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -verify-machineinstrs -ppc-disable-perfect-shuffle=false < %s | FileCheck %s
 
 ; TODO: Fix this case when disabling perfect shuffle
@@ -7,25 +8,25 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 ; Function Attrs: nounwind
 define <2 x i32> @test1(<4 x i32> %wide.vec) #0 {
+; CHECK-LABEL: test1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd 0, 34
+; CHECK-NEXT:    xxmrghw 34, 34, 0
+; CHECK-NEXT:    blr
 entry:
   %strided.vec = shufflevector <4 x i32> %wide.vec, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
   ret <2 x i32> %strided.vec
-
-; CHECK-LABEL: @test1
-; CHECK: xxswapd 0, 34
-; CHECK: xxmrghw 34, 34, 0
-; CHECK: blr
 }
 
 ; Function Attrs: nounwind
 define <16 x i8> @test2(<16 x i8> %wide.vec) #0 {
+; CHECK-LABEL: test2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsldwi 34, 34, 34, 3
+; CHECK-NEXT:    blr
 entry:
   %strided.vec = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 8, i32 9, i32 10, i32 11>
   ret <16 x i8> %strided.vec
-
-; CHECK-LABEL: @test2
-; CHECK: xxsldwi 34, 34, 34, 3
-; CHECK: blr
 }
 
 attributes #0 = { nounwind "target-cpu"="pwr7" }