[llvm] 4a70981 - AMDGPU/gfx12: Minor documentation update (#96079)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 19 07:49:21 PDT 2024
Author: Nicolai Hähnle
Date: 2024-06-19T16:49:18+02:00
New Revision: 4a70981d21f8d9e9476032c239be1d346488a7dc
URL: https://github.com/llvm/llvm-project/commit/4a70981d21f8d9e9476032c239be1d346488a7dc
DIFF: https://github.com/llvm/llvm-project/commit/4a70981d21f8d9e9476032c239be1d346488a7dc.diff
LOG: AMDGPU/gfx12: Minor documentation update (#96079)
Added:
Modified:
llvm/docs/AMDGPUUsage.rst
Removed:
################################################################################
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index b7ec1b51ee247..5a16457412d24 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -4811,10 +4811,10 @@ The fields used by CP for code objects before V3 also match those specified in
- vgprs_used = align(arch_vgprs, 4)
+ acc_vgprs
- max(0, ceil(vgprs_used / 8) - 1)
- GFX10-GFX11 (wavefront size 64)
+ GFX10-GFX12 (wavefront size 64)
- max_vgpr 1..256
- max(0, ceil(vgprs_used / 4) - 1)
- GFX10-GFX11 (wavefront size 32)
+ GFX10-GFX12 (wavefront size 32)
- max_vgpr 1..256
- max(0, ceil(vgprs_used / 8) - 1)
@@ -4848,7 +4848,7 @@ The fields used by CP for code objects before V3 also match those specified in
GFX9
- sgprs_used 0..112
- 2 * max(0, ceil(sgprs_used / 16) - 1)
- GFX10-GFX11
+ GFX10-GFX12
Reserved, must be 0.
(128 SGPRs always
allocated.)
@@ -5028,7 +5028,7 @@ The fields used by CP for code objects before V3 also match those specified in
``COMPUTE_PGM_RSRC1.CDBG_USER``.
26 1 bit FP16_OVFL GFX6-GFX8
Reserved, must be 0.
- GFX9-GFX11
+ GFX9-GFX12
Wavefront starts execution
with specified fp16 overflow
mode.
@@ -5047,7 +5047,7 @@ The fields used by CP for code objects before V3 also match those specified in
28:27 2 bits Reserved, must be 0.
29 1 bit WGP_MODE GFX6-GFX9
Reserved, must be 0.
- GFX10-GFX11
+ GFX10-GFX12
- If 0 execute work-groups in
CU wavefront execution mode.
- If 1 execute work-groups on
@@ -5059,7 +5059,7 @@ The fields used by CP for code objects before V3 also match those specified in
``COMPUTE_PGM_RSRC1.WGP_MODE``.
30 1 bit MEM_ORDERED GFX6-GFX9
Reserved, must be 0.
- GFX10-GFX11
+ GFX10-GFX12
Controls the behavior of the
s_waitcnt's vmcnt and vscnt
counters.
@@ -5082,7 +5082,7 @@ The fields used by CP for code objects before V3 also match those specified in
``COMPUTE_PGM_RSRC1.MEM_ORDERED``.
31 1 bit FWD_PROGRESS GFX6-GFX9
Reserved, must be 0.
- GFX10-GFX11
+ GFX10-GFX12
- If 0 execute SIMD wavefronts
using oldest first policy.
- If 1 execute SIMD wavefronts to
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