[llvm] [RISCV] Mark all registers marked isConstant as reserved (PR #96002)

[Craig Topper via llvm-commits]

================
@@ -104,14 +104,16 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   BitVector Reserved(getNumRegs());
   auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
 
-  // Mark any registers requested to be reserved as such
   for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
----------------
topperc wrote:

I find it odd that this loop was looping over more than just the GPRs originally. We could maybe save some compile time by not checking every register, but this patch now requires us to check every register.

https://github.com/llvm/llvm-project/pull/96002