[llvm] dd1d2b7 - [llvm][CodeGen] Fix failure in window scheduler caused by phi (#95900)

[via llvm-commits]

Author: Hua Tian
Date: 2024-06-19T15:15:37+08:00
New Revision: dd1d2b7cb083e870174d50627870c835d1e118e6

URL: https://github.com/llvm/llvm-project/commit/dd1d2b7cb083e870174d50627870c835d1e118e6
DIFF: https://github.com/llvm/llvm-project/commit/dd1d2b7cb083e870174d50627870c835d1e118e6.diff

LOG: [llvm][CodeGen] Fix failure in window scheduler caused by phi (#95900)

In certain cases, the register passed with the kernel MBB in phi are not
defined within the kernel MBB. This patch adds the corresponding handling.

Added: 
    llvm/test/CodeGen/Hexagon/swp-ws-phi.mir

Modified: 
    llvm/lib/CodeGen/WindowScheduler.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/WindowScheduler.cpp b/llvm/lib/CodeGen/WindowScheduler.cpp
index 418309bc9dbf5..7a86351a1f4e3 100644
--- a/llvm/lib/CodeGen/WindowScheduler.cpp
+++ b/llvm/lib/CodeGen/WindowScheduler.cpp
@@ -533,9 +533,12 @@ void WindowScheduler::schedulePhi(int Offset, unsigned &II) {
     // The anti-dependency of phi need to be handled separately in the same way.
     if (Register AntiReg = getAntiRegister(&Phi)) {
       auto *AntiMI = MRI->getVRegDef(AntiReg);
-      auto AntiCycle = getOriCycle(AntiMI);
-      if (getOriStage(getOriMI(AntiMI), Offset) == 0)
-        LateCycle = std::min(LateCycle, AntiCycle);
+      // AntiReg may be defined outside the kernel MBB.
+      if (AntiMI->getParent() == MBB) {
+        auto AntiCycle = getOriCycle(AntiMI);
+        if (getOriStage(getOriMI(AntiMI), Offset) == 0)
+          LateCycle = std::min(LateCycle, AntiCycle);
+      }
     }
     // If there is no limit to the late cycle, a default value is given.
     if (LateCycle == INT_MAX)
@@ -683,7 +686,7 @@ Register WindowScheduler::getAntiRegister(MachineInstr *Phi) {
   for (auto MO : Phi->uses()) {
     if (MO.isReg())
       AntiReg = MO.getReg();
-    else if (MO.isMBB() && MO.getMBB()->getNumber() == MBB->getNumber())
+    else if (MO.isMBB() && MO.getMBB() == MBB)
       return AntiReg;
   }
   return 0;

diff  --git a/llvm/test/CodeGen/Hexagon/swp-ws-phi.mir b/llvm/test/CodeGen/Hexagon/swp-ws-phi.mir
new file mode 100644
index 0000000000000..7897a02b43f38
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/swp-ws-phi.mir
@@ -0,0 +1,41 @@
+# REQUIRES: asserts
+# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \
+# RUN: -window-sched=force -filetype=null 2>&1 | FileCheck %s
+
+# CHECK: Window scheduling is not needed!
+# CHECK-LABEL: body:             |
+# CHECK: bb.0:
+# CHECK: [[REG:%[0-9]+]]:intregs = A2_tfrsi 0
+# CHECK: bb.2:
+# CHECK: {{%[0-9]+}}:intregs = PHI {{%[0-9]+}}, %bb.0, [[REG]], %bb.2
+
+---
+name:            poll_for_response
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    successors: %bb.2(0x80000000)
+    liveins: $r0, $r1
+  
+    %0:intregs = COPY $r1
+    %1:intregs = COPY $r0
+    %2:intregs = A2_tfrsi 0
+    J2_loop0i %bb.2, 2, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
+    J2_jump %bb.2, implicit-def dead $pc
+  
+  bb.1:
+    PS_jmpret $r31, implicit-def dead $pc
+  
+  bb.2:
+    successors: %bb.1(0x04000000), %bb.2(0x7c000000)
+  
+    %3:intregs = PHI %1, %bb.0, %2, %bb.2
+    %4:intregs = PHI %2, %bb.0, %5, %bb.2
+    %6:intregs = S2_lsr_i_r %3, 1
+    S2_storerb_io %0, 0, killed %6
+    S4_storerb_rr %0, %4, 0, %2
+    %5:intregs = A2_tfrsi 1
+    ENDLOOP0 %bb.2, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
+    J2_jump %bb.1, implicit-def $pc
+
+...