[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

[Pengcheng Wang via llvm-commits]

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@@ -358,3 +358,21 @@
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 -march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
 // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr3-rv32 | FileCheck -check-prefix=MCPU-SYNTACORE-SCR3-RV32 %s
+// MCPU-SYNTACORE-SCR3-RV32: "-target-cpu" "syntacore-scr3-rv32"
+// MCPU-SYNTACORE-SCR3-RV32: "-target-feature" "+m" "-target-feature" "+c"
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wangpc-pp wrote:

One `-target-feature` one line please.

https://github.com/llvm/llvm-project/pull/95953