[clang] [llvm] Split fmv and extensions (PR #92882)
Tomas Matheson via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 18 14:22:36 PDT 2024
https://github.com/tmatheson-arm updated https://github.com/llvm/llvm-project/pull/92882
>From 76ccb775de5103dde3b59b838ba3f71be367418d Mon Sep 17 00:00:00 2001
From: Tomas Matheson <tomas.matheson at arm.com>
Date: Tue, 21 May 2024 09:36:48 +0100
Subject: [PATCH 1/7] Separate FMV and Extensions
---
clang/include/clang/AST/ASTContext.h | 3 -
clang/include/clang/Basic/TargetInfo.h | 5 -
clang/lib/AST/ASTContext.cpp | 31 ++-
clang/lib/Basic/Targets/AArch64.cpp | 97 +++++---
clang/lib/Basic/Targets/AArch64.h | 1 -
clang/lib/CodeGen/CGBuiltin.cpp | 2 +-
clang/lib/CodeGen/Targets/AArch64.cpp | 2 +-
clang/test/CodeGen/aarch64-fmv-dependencies.c | 92 ++++----
clang/test/CodeGen/attr-target-version.c | 46 ++--
.../llvm/TargetParser/AArch64TargetParser.h | 39 +++-
llvm/lib/Target/AArch64/AArch64.td | 1 +
llvm/lib/Target/AArch64/AArch64FMV.td | 78 +++++++
llvm/lib/Target/AArch64/AArch64Features.td | 211 ++++--------------
llvm/lib/TargetParser/AArch64TargetParser.cpp | 39 +++-
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 36 ++-
15 files changed, 373 insertions(+), 310 deletions(-)
create mode 100644 llvm/lib/Target/AArch64/AArch64FMV.td
diff --git a/clang/include/clang/AST/ASTContext.h b/clang/include/clang/AST/ASTContext.h
index 2ce2b810d3636..e2ed06a3d8b6b 100644
--- a/clang/include/clang/AST/ASTContext.h
+++ b/clang/include/clang/AST/ASTContext.h
@@ -3194,9 +3194,6 @@ class ASTContext : public RefCountedBase<ASTContext> {
/// valid feature names.
ParsedTargetAttr filterFunctionTargetAttrs(const TargetAttr *TD) const;
- std::vector<std::string>
- filterFunctionTargetVersionAttrs(const TargetVersionAttr *TV) const;
-
void getFunctionFeatureMap(llvm::StringMap<bool> &FeatureMap,
const FunctionDecl *) const;
void getFunctionFeatureMap(llvm::StringMap<bool> &FeatureMap,
diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h
index 8a6511b9ced83..9b0ae2102e098 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1400,11 +1400,6 @@ class TargetInfo : public TransferrableTargetInfo,
return true;
}
- /// For given feature return dependent ones.
- virtual StringRef getFeatureDependencies(StringRef Feature) const {
- return StringRef();
- }
-
struct BranchProtectionInfo {
LangOptions::SignReturnAddressScopeKind SignReturnAddr;
LangOptions::SignReturnAddressKeyKind SignKey;
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 52eab5feb062b..bbf72b1440e91 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -87,6 +87,7 @@
#include "llvm/Support/MD5.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/TargetParser/AArch64TargetParser.h"
#include "llvm/TargetParser/Triple.h"
#include <algorithm>
#include <cassert>
@@ -13664,16 +13665,23 @@ QualType ASTContext::getCorrespondingSignedFixedPointType(QualType Ty) const {
}
}
+// Given a list of FMV features, add each of their backend features to the list.
+static void
+GetFMVBackendFeaturesFor(const llvm::SmallVector<StringRef, 8> FMVFeatStrings,
+ std::vector<std::string>& BackendFeats) {
+ for (auto &F : FMVFeatStrings)
+ if (auto FMVExt = llvm::AArch64::parseFMVExtension(F))
+ for (auto F : FMVExt->getImpliedFeatures())
+ BackendFeats.push_back(F.str());
+}
+
std::vector<std::string> ASTContext::filterFunctionTargetVersionAttrs(
const TargetVersionAttr *TV) const {
assert(TV != nullptr);
llvm::SmallVector<StringRef, 8> Feats;
std::vector<std::string> ResFeats;
TV->getFeatures(Feats);
- for (auto &Feature : Feats)
- if (Target->validateCpuSupports(Feature.str()))
- // Use '?' to mark features that came from TargetVersion.
- ResFeats.push_back("?" + Feature.str());
+ GetFMVBackendFeaturesFor(Feats, ResFeats);
return ResFeats;
}
@@ -13735,13 +13743,11 @@ void ASTContext::getFunctionFeatureMap(llvm::StringMap<bool> &FeatureMap,
} else if (const auto *TC = FD->getAttr<TargetClonesAttr>()) {
std::vector<std::string> Features;
if (Target->getTriple().isAArch64()) {
- // TargetClones for AArch64
llvm::SmallVector<StringRef, 8> Feats;
TC->getFeatures(Feats, GD.getMultiVersionIndex());
- for (StringRef Feat : Feats)
- if (Target->validateCpuSupports(Feat.str()))
- // Use '?' to mark features that came from AArch64 TargetClones.
- Features.push_back("?" + Feat.str());
+ GetFMVBackendFeaturesFor(Feats, Features);
+
+ // Combine with the features from the Target, not expanded
Features.insert(Features.begin(),
Target->getTargetOpts().FeaturesAsWritten.begin(),
Target->getTargetOpts().FeaturesAsWritten.end());
@@ -13754,11 +13760,14 @@ void ASTContext::getFunctionFeatureMap(llvm::StringMap<bool> &FeatureMap,
}
Target->initFeatureMap(FeatureMap, getDiagnostics(), TargetCPU, Features);
} else if (const auto *TV = FD->getAttr<TargetVersionAttr>()) {
- std::vector<std::string> Feats = filterFunctionTargetVersionAttrs(TV);
+ llvm::SmallVector<StringRef, 8> Feats;
+ TV->getFeatures(Feats);
+ std::vector<std::string> Features;
+ GetFMVBackendFeaturesFor(Feats, Features);
Feats.insert(Feats.begin(),
Target->getTargetOpts().FeaturesAsWritten.begin(),
Target->getTargetOpts().FeaturesAsWritten.end());
- Target->initFeatureMap(FeatureMap, getDiagnostics(), TargetCPU, Feats);
+ Target->initFeatureMap(FeatureMap, getDiagnostics(), TargetCPU, Features);
} else {
FeatureMap = Target->getTargetOpts().FeatureMap;
}
diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
index 5db1ce78c657f..9077019affd35 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -659,34 +659,30 @@ AArch64TargetInfo::getVScaleRange(const LangOptions &LangOpts) const {
unsigned AArch64TargetInfo::multiVersionSortPriority(StringRef Name) const {
if (Name == "default")
return 0;
- if (auto Ext = llvm::AArch64::parseArchExtension(Name))
- return Ext->FmvPriority;
+ if (auto Ext = llvm::AArch64::parseFMVExtension(Name))
+ return Ext->Priority;
return 0;
}
unsigned AArch64TargetInfo::multiVersionFeatureCost() const {
// Take the maximum priority as per feature cost, so more features win.
- return llvm::AArch64::ExtensionInfo::MaxFMVPriority;
+ constexpr unsigned MaxFMVPriority = 1000;
+ return MaxFMVPriority;
}
bool AArch64TargetInfo::doesFeatureAffectCodeGen(StringRef Name) const {
- if (auto Ext = llvm::AArch64::parseArchExtension(Name))
- return !Ext->DependentFeatures.empty();
+ // FMV extensions which imply no backend features do not affect codegen.
+ if (auto Ext = llvm::AArch64::parseFMVExtension(Name))
+ return !Ext->Features.empty();
return false;
}
-StringRef AArch64TargetInfo::getFeatureDependencies(StringRef Name) const {
- if (auto Ext = llvm::AArch64::parseArchExtension(Name))
- return Ext->DependentFeatures;
- return StringRef();
-}
-
bool AArch64TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
// CPU features might be separated by '+', extract them and check
llvm::SmallVector<StringRef, 8> Features;
FeatureStr.split(Features, "+");
for (auto &Feature : Features)
- if (!llvm::AArch64::parseArchExtension(Feature.trim()).has_value())
+ if (!llvm::AArch64::parseFMVExtension(Feature.trim()).has_value())
return false;
return true;
}
@@ -1066,31 +1062,62 @@ bool AArch64TargetInfo::initFeatureMap(
}
}
- // Process target and dependent features. This is done in two loops collecting
- // them into UpdatedFeaturesVec: first to add dependent '+'features, second to
- // add target '+/-'features that can later disable some of features added on
- // the first loop. Function Multi Versioning features begin with '?'.
- for (const auto &Feature : FeaturesVec)
- if (((Feature[0] == '?' || Feature[0] == '+')) &&
- AArch64TargetInfo::doesFeatureAffectCodeGen(Feature.substr(1))) {
- StringRef DepFeatures =
- AArch64TargetInfo::getFeatureDependencies(Feature.substr(1));
- SmallVector<StringRef, 1> AttrFeatures;
- DepFeatures.split(AttrFeatures, ",");
- for (auto F : AttrFeatures)
- UpdatedFeaturesVec.push_back(F.str());
+ // Special cases which rely on dependency expansion at this stage
+ for(auto F : FeaturesVec) {
+ // Crypto is the only one we don't want passed through
+ if(F == "+crypto") {
+ UpdatedFeaturesVec.emplace_back("+aes");
+ UpdatedFeaturesVec.emplace_back("+sha2");
+ } else {
+ UpdatedFeaturesVec.emplace_back(F);
}
- for (const auto &Feature : FeaturesVec)
- if (Feature[0] != '?') {
- std::string UpdatedFeature = Feature;
- if (Feature[0] == '+') {
- std::optional<llvm::AArch64::ExtensionInfo> Extension =
- llvm::AArch64::parseArchExtension(Feature.substr(1));
- if (Extension)
- UpdatedFeature = Extension->Feature.str();
- }
- UpdatedFeaturesVec.push_back(UpdatedFeature);
+
+ if(F == "+sve") {
+ UpdatedFeaturesVec.emplace_back("+sve");
+ UpdatedFeaturesVec.emplace_back("+fullfp16");
+ UpdatedFeaturesVec.emplace_back("+neon");
+ UpdatedFeaturesVec.emplace_back("+fp-armv8");
+ }
+ else if(F == "+sve2") {
+ UpdatedFeaturesVec.emplace_back("+sve");
+ UpdatedFeaturesVec.emplace_back("+fullfp16");
+ }
+ else if(F == "+sve2p1") {
+ UpdatedFeaturesVec.emplace_back("+sve2");
+ UpdatedFeaturesVec.emplace_back("+sve");
+ }
+ else if(F == "+sve2-aes") {
+ UpdatedFeaturesVec.emplace_back("+sve2");
+ UpdatedFeaturesVec.emplace_back("+sve");
}
+ else if(F == "+sve2-bitperm") {
+ UpdatedFeaturesVec.emplace_back("+sve2");
+ UpdatedFeaturesVec.emplace_back("+sve");
+ }
+ else if(F == "+sve2-sha3") {
+ UpdatedFeaturesVec.emplace_back("+sve2");
+ UpdatedFeaturesVec.emplace_back("+sve");
+ }
+ else if(F == "+sve2-sm4") {
+ UpdatedFeaturesVec.emplace_back("+sve2");
+ UpdatedFeaturesVec.emplace_back("+sve");
+ }
+ else if(F == "+sme") {
+ UpdatedFeaturesVec.emplace_back("+bf16");
+ }
+ else if(F == "+sme2") {
+ UpdatedFeaturesVec.emplace_back("+sme");
+ UpdatedFeaturesVec.emplace_back("+bf16");
+ }
+ else if(F == "+sme-i16i64") {
+ UpdatedFeaturesVec.emplace_back("+sme");
+ UpdatedFeaturesVec.emplace_back("+bf16");
+ }
+ else if(F == "+sme2p1") {
+ UpdatedFeaturesVec.emplace_back("+sme2");
+ UpdatedFeaturesVec.emplace_back("+sme");
+ }
+ }
return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec);
}
diff --git a/clang/lib/Basic/Targets/AArch64.h b/clang/lib/Basic/Targets/AArch64.h
index 12fb50286f751..6bc71e4f330f8 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -155,7 +155,6 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo {
std::optional<std::pair<unsigned, unsigned>>
getVScaleRange(const LangOptions &LangOpts) const override;
bool doesFeatureAffectCodeGen(StringRef Name) const override;
- StringRef getFeatureDependencies(StringRef Name) const override;
bool validateCpuSupports(StringRef FeatureStr) const override;
bool hasFeature(StringRef Feature) const override;
void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index ba94bf89e4751..8cec39b19f23a 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -14176,7 +14176,7 @@ Value *CodeGenFunction::EmitAArch64CpuSupports(const CallExpr *E) {
ArgStr.split(Features, "+");
for (auto &Feature : Features) {
Feature = Feature.trim();
- if (!llvm::AArch64::parseArchExtension(Feature))
+ if (!llvm::AArch64::parseFMVExtension(Feature))
return Builder.getFalse();
if (Feature != "default")
Features.push_back(Feature);
diff --git a/clang/lib/CodeGen/Targets/AArch64.cpp b/clang/lib/CodeGen/Targets/AArch64.cpp
index 9aa3ea75681b3..674246da86b85 100644
--- a/clang/lib/CodeGen/Targets/AArch64.cpp
+++ b/clang/lib/CodeGen/Targets/AArch64.cpp
@@ -962,7 +962,7 @@ void AArch64ABIInfo::appendAttributeMangling(StringRef AttrStr,
llvm::SmallDenseSet<StringRef, 8> UniqueFeats;
for (auto &Feat : Features)
- if (auto Ext = llvm::AArch64::parseArchExtension(Feat))
+ if (auto Ext = llvm::AArch64::parseFMVExtension(Feat))
if (UniqueFeats.insert(Ext->Name).second)
Out << 'M' << Ext->Name;
}
diff --git a/clang/test/CodeGen/aarch64-fmv-dependencies.c b/clang/test/CodeGen/aarch64-fmv-dependencies.c
index ec599e1b3fa76..e39c7adbe4a9b 100644
--- a/clang/test/CodeGen/aarch64-fmv-dependencies.c
+++ b/clang/test/CodeGen/aarch64-fmv-dependencies.c
@@ -192,49 +192,49 @@ int caller() {
return fmv();
}
-// CHECK: attributes #[[ATTR0:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a"
-// CHECK: attributes #[[bf16_ebf16:[0-9]+]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+v8a"
-// CHECK: attributes #[[bti:[0-9]+]] = { {{.*}} "target-features"="+bti,+fp-armv8,+neon,+outline-atomics,+v8a"
-// CHECK: attributes #[[crc:[0-9]+]] = { {{.*}} "target-features"="+crc,+fp-armv8,+neon,+outline-atomics,+v8a"
-// CHECK: attributes #[[dit:[0-9]+]] = { {{.*}} "target-features"="+dit,+fp-armv8,+neon,+outline-atomics,+v8a"
-// CHECK: attributes #[[dotprod:[0-9]+]] = { {{.*}} "target-features"="+dotprod,+fp-armv8,+neon,+outline-atomics,+v8a"
-// CHECK: attributes #[[dpb:[0-9]+]] = { {{.*}} "target-features"="+ccpp,+fp-armv8,+neon,+outline-atomics,+v8a"
-// CHECK: attributes #[[dpb2:[0-9]+]] = { {{.*}} "target-features"="+ccdp,+ccpp,+fp-armv8,+neon,+outline-atomics,+v8a"
-// CHECK: attributes #[[f32mm:[0-9]+]] = { {{.*}} "target-features"="+f32mm,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a"
-// CHECK: attributes #[[f64mm:[0-9]+]] = { {{.*}} "target-features"="+f64mm,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a"
-// CHECK: attributes #[[fcma:[0-9]+]] = { {{.*}} "target-features"="+complxnum,+fp-armv8,+neon,+outline-atomics,+v8a"
-// CHECK: attributes #[[flagm:[0-9]+]] = { {{.*}} "target-features"="+flagm,+fp-armv8,+neon,+outline-atomics,+v8a"
-// CHECK: attributes #[[flagm2:[0-9]+]] = { {{.*}} "target-features"="+altnzcv,+flagm,+fp-armv8,+neon,+outline-atomics,+v8a"
-// CHECK: attributes #[[fp16:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+v8a"
-// CHECK: attributes #[[fp16fml:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+fp16fml,+fullfp16,+neon,+outline-atomics,+v8a"
-// CHECK: attributes #[[frintts:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+fptoint,+neon,+outline-atomics,+v8a"
-// CHECK: attributes #[[i8mm:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+i8mm,+neon,+outline-atomics,+v8a"
-// CHECK: attributes #[[jscvt:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+jsconv,+neon,+outline-atomics,+v8a"
-// CHECK: attributes #[[ls64_accdata:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+ls64,+neon,+outline-atomics,+v8a"
-// CHECK: attributes #[[lse:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+lse,+neon,+outline-atomics,+v8a"
-// CHECK: attributes #[[memtag2:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+mte,+neon,+outline-atomics,+v8a"
-// CHECK: attributes #[[mops:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+mops,+neon,+outline-atomics,+v8a"
-// CHECK: attributes #[[pmull:[0-9]+]] = { {{.*}} "target-features"="+aes,+fp-armv8,+neon,+outline-atomics,+v8a"
-// CHECK: attributes #[[predres:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+predres,+v8a"
-// CHECK: attributes #[[rcpc:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rcpc,+v8a"
-// CHECK: attributes #[[rcpc3:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rcpc,+rcpc3,+v8a"
-// CHECK: attributes #[[rdm:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rdm,+v8a"
-// CHECK: attributes #[[rng:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rand,+v8a"
-// CHECK: attributes #[[sb:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+sb,+v8a"
-// CHECK: attributes #[[sha2:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+sha2,+v8a"
-// CHECK: attributes #[[sha3:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+sha2,+sha3,+v8a"
-// CHECK: attributes #[[sm4:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+sm4,+v8a"
-// CHECK: attributes #[[sme:[0-9]+]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+sme,+v8a"
-// CHECK: attributes #[[sme_f64f64:[0-9]+]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+sme,+sme-f64f64,+v8a"
-// CHECK: attributes #[[sme_i16i64:[0-9]+]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+sme,+sme-i16i64,+v8a"
-// CHECK: attributes #[[sme2:[0-9]+]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+sme,+sme2,+v8a"
-// CHECK: attributes #[[ssbs2:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+ssbs,+v8a"
-// CHECK: attributes #[[sve:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a"
-// CHECK: attributes #[[sve_bf16_ebf16:[0-9]+]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a"
-// CHECK: attributes #[[sve_i8mm:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+i8mm,+neon,+outline-atomics,+sve,+v8a"
-// CHECK: attributes #[[sve2:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+v8a"
-// CHECK: attributes #[[sve2_aes_sve2_pmull128:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-aes,+v8a"
-// CHECK: attributes #[[sve2_bitperm:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-bitperm,+v8a"
-// CHECK: attributes #[[sve2_sha3:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-sha3,+v8a"
-// CHECK: attributes #[[sve2_sm4:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-sm4,+v8a"
-// CHECK: attributes #[[wfxt:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a,+wfxt"
+// CHECK: attributes #[[ATTR0]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[bf16_ebf16]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[bti]] = { {{.*}} "target-features"="+bti,+fp-armv8,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[crc]] = { {{.*}} "target-features"="+crc,+fp-armv8,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[dit]] = { {{.*}} "target-features"="+dit,+fp-armv8,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[dotprod]] = { {{.*}} "target-features"="+dotprod,+fp-armv8,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[dpb]] = { {{.*}} "target-features"="+ccpp,+fp-armv8,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[dpb2]] = { {{.*}} "target-features"="+ccdp,+ccpp,+fp-armv8,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[f32mm]] = { {{.*}} "target-features"="+f32mm,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a"
+// CHECK: attributes #[[f64mm]] = { {{.*}} "target-features"="+f64mm,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a"
+// CHECK: attributes #[[fcma]] = { {{.*}} "target-features"="+complxnum,+fp-armv8,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[flagm]] = { {{.*}} "target-features"="+flagm,+fp-armv8,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[flagm2]] = { {{.*}} "target-features"="+altnzcv,+flagm,+fp-armv8,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[fp16]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[fp16fml]] = { {{.*}} "target-features"="+fp-armv8,+fp16fml,+fullfp16,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[frintts]] = { {{.*}} "target-features"="+fp-armv8,+fptoint,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[i8mm]] = { {{.*}} "target-features"="+fp-armv8,+i8mm,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[jscvt]] = { {{.*}} "target-features"="+fp-armv8,+jsconv,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[ls64_accdata]] = { {{.*}} "target-features"="+fp-armv8,+ls64,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[lse]] = { {{.*}} "target-features"="+fp-armv8,+lse,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[memtag2]] = { {{.*}} "target-features"="+fp-armv8,+mte,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[mops]] = { {{.*}} "target-features"="+fp-armv8,+mops,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[pmull]] = { {{.*}} "target-features"="+aes,+fp-armv8,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[predres]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+predres,+v8a"
+// CHECK: attributes #[[rcpc]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rcpc,+v8a"
+// CHECK: attributes #[[rcpc3]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rcpc,+rcpc3,+v8a"
+// CHECK: attributes #[[rdm]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rdm,+v8a"
+// CHECK: attributes #[[rng]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rand,+v8a"
+// CHECK: attributes #[[sb]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+sb,+v8a"
+// CHECK: attributes #[[sha2]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+sha2,+v8a"
+// CHECK: attributes #[[sha3]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+sha2,+sha3,+v8a"
+// CHECK: attributes #[[sm4]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+sm4,+v8a"
+// CHECK: attributes #[[sme]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+sme,+v8a"
+// CHECK: attributes #[[sme_f64f64]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+sme,+sme-f64f64,+v8a"
+// CHECK: attributes #[[sme_i16i64]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+sme,+sme-i16i64,+v8a"
+// CHECK: attributes #[[sme2]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+sme,+sme2,+v8a"
+// CHECK: attributes #[[ssbs2]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+ssbs,+v8a"
+// CHECK: attributes #[[sve]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a"
+// CHECK: attributes #[[sve_bf16_ebf16]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a"
+// CHECK: attributes #[[sve_i8mm]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+i8mm,+neon,+outline-atomics,+sve,+v8a"
+// CHECK: attributes #[[sve2]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+v8a"
+// CHECK: attributes #[[sve2_aes_sve2_pmull128]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-aes,+v8a"
+// CHECK: attributes #[[sve2_bitperm]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-bitperm,+v8a"
+// CHECK: attributes #[[sve2_sha3]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-sha3,+v8a"
+// CHECK: attributes #[[sve2_sm4]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-sm4,+v8a"
+// CHECK: attributes #[[wfxt]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a,+wfxt"
diff --git a/clang/test/CodeGen/attr-target-version.c b/clang/test/CodeGen/attr-target-version.c
index 3597711333d34..75f8734e5aaf3 100644
--- a/clang/test/CodeGen/attr-target-version.c
+++ b/clang/test/CodeGen/attr-target-version.c
@@ -1129,42 +1129,42 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
// CHECK-NOFMV-NEXT: ret i32 0
//
//.
-// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+flagm,+fp16fml,+fullfp16,+neon,+rand,-fp-armv8,-v9.5a" }
+// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+flagm,+fp-armv8,+fp16fml,+fullfp16,+neon,+rand,-v9.5a" }
// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+altnzcv,+bf16,+flagm,+sme,+sme-i16i64,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+lse,+neon,+sha2,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+dotprod,+ls64,+neon,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp16fml,+fullfp16,+neon,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,-fp-armv8,-v9.5a" }
+// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+lse,+neon,+sha2,-v9.5a" }
+// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+dotprod,+fp-armv8,+ls64,+neon,-v9.5a" }
+// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fp16fml,+fullfp16,+neon,-v9.5a" }
+// CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,-v9.5a" }
// CHECK: attributes #[[ATTR6]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,-fp-armv8,-v9.5a" }
// CHECK: attributes #[[ATTR7]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,-fp-armv8,-v9.5a" }
// CHECK: attributes #[[ATTR8]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sme,+sme2,-fp-armv8,-v9.5a" }
// CHECK: attributes #[[ATTR9:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fp-armv8,-v9.5a" }
// CHECK: attributes #[[ATTR10]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ccpp,-fp-armv8,-v9.5a" }
// CHECK: attributes #[[ATTR11]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR12]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon,-fp-armv8,-v9.5a" }
+// CHECK: attributes #[[ATTR12]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,-v9.5a" }
// CHECK: attributes #[[ATTR13]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sb,-fp-armv8,-v9.5a" }
// CHECK: attributes #[[ATTR14]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+mops,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+dotprod,+neon,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR16]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon,+sve,-fp-armv8,-v9.5a" }
+// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+dotprod,+fp-armv8,+neon,-v9.5a" }
+// CHECK: attributes #[[ATTR16]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,-v9.5a" }
// CHECK: attributes #[[ATTR17]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+lse,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR18]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,+rdm,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR19:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+jsconv,+neon,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR20:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,+rdm,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR21]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+jsconv,+neon,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR22]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+aes,+f64mm,+fullfp16,+neon,+sve,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR23]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+complxnum,+fullfp16,+neon,+rdm,+sme,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR24]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f32mm,+fullfp16,+i8mm,+neon,+sha2,+sha3,+sve,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR25]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+dit,+fullfp16,+neon,+sve,-fp-armv8,-v9.5a" }
+// CHECK: attributes #[[ATTR18]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+rdm,-v9.5a" }
+// CHECK: attributes #[[ATTR19:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+jsconv,+neon,-v9.5a" }
+// CHECK: attributes #[[ATTR20:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+rdm,-v9.5a" }
+// CHECK: attributes #[[ATTR21]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+jsconv,+neon,-v9.5a" }
+// CHECK: attributes #[[ATTR22]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+aes,+f64mm,+fp-armv8,+fullfp16,+neon,+sve,-v9.5a" }
+// CHECK: attributes #[[ATTR23]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+complxnum,+fp-armv8,+fullfp16,+neon,+rdm,+sme,-v9.5a" }
+// CHECK: attributes #[[ATTR24]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f32mm,+fp-armv8,+fullfp16,+i8mm,+neon,+sha2,+sha3,+sve,-v9.5a" }
+// CHECK: attributes #[[ATTR25]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+dit,+fp-armv8,+fullfp16,+neon,+sve,-v9.5a" }
// CHECK: attributes #[[ATTR26]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ccpp,+rcpc,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR27]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ccdp,+ccpp,+jsconv,+neon,-fp-armv8,-v9.5a" }
+// CHECK: attributes #[[ATTR27]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ccdp,+ccpp,+fp-armv8,+jsconv,+neon,-v9.5a" }
// CHECK: attributes #[[ATTR28]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fptoint,+rcpc,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR29]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+fullfp16,+neon,+sve,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR30]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon,+sve,+sve2,+sve2-aes,+sve2-sha3,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR31]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon,+sve,+sve2,+sve2-aes,+sve2-bitperm,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR32]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+mte,+neon,+sve,+sve2,+sve2-sm4,-fp-armv8,-v9.5a" }
+// CHECK: attributes #[[ATTR29]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+fp-armv8,+fullfp16,+neon,+sve,-v9.5a" }
+// CHECK: attributes #[[ATTR30]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-aes,+sve2-sha3,-v9.5a" }
+// CHECK: attributes #[[ATTR31]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-aes,+sve2-bitperm,-v9.5a" }
+// CHECK: attributes #[[ATTR32]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+mte,+neon,+sve,+sve2,+sve2-sm4,-v9.5a" }
// CHECK: attributes #[[ATTR33]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+mops,+mte,+rcpc,+rcpc3,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR34]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,+sm4,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR35]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+lse,+neon,+rdm,-fp-armv8,-v9.5a" }
+// CHECK: attributes #[[ATTR34]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+sm4,-v9.5a" }
+// CHECK: attributes #[[ATTR35]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+lse,+neon,+rdm,-v9.5a" }
//.
// CHECK-NOFMV: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" }
// CHECK-NOFMV: attributes #[[ATTR1:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" }
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index b3fff3c99025a..cd9059d07869f 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -19,6 +19,8 @@
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/Support/VersionTuple.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/TargetParser/SubtargetFeature.h"
#include <array>
#include <vector>
@@ -120,18 +122,30 @@ struct ExtensionInfo {
// extensions representation in the bitfield.
StringRef Feature; // -mattr enable string, e.g. "+spe"
StringRef NegFeature; // -mattr disable string, e.g. "-spe"
- CPUFeatures CPUFeature; // Function Multi Versioning (FMV) bitfield value
- // set in __aarch64_cpu_features
- StringRef DependentFeatures; // FMV enabled features string,
- // e.g. "+dotprod,+fp-armv8,+neon"
- unsigned FmvPriority; // FMV feature priority
- static constexpr unsigned MaxFMVPriority =
- 1000; // Maximum priority for FMV feature
};
#define EMIT_EXTENSIONS
#include "llvm/TargetParser/AArch64TargetParserDef.inc"
+
+struct FMVInfo {
+ StringRef Name; // The target_version/target_clones spelling.
+ CPUFeatures Bit; // Index of the bit in the FMV feature bitset.
+ StringRef Features; // List of SubtargetFeatures to enable.
+ unsigned Priority; // FMV priority.
+ FMVInfo(StringRef Name, CPUFeatures Bit, StringRef Features,
+ unsigned Priority)
+ : Name(Name), Bit(Bit), Features(Features), Priority(Priority){};
+
+ SmallVector<StringRef, 8> getImpliedFeatures() {
+ SmallVector<StringRef, 8> Feats;
+ Features.split(Feats, ',', -1, false); // discard empty strings
+ return Feats;
+ }
+};
+
+const std::vector<FMVInfo>& getFMVInfo();
+
struct ExtensionSet {
// Set of extensions which are currently enabled.
ExtensionBitset Enabled;
@@ -172,6 +186,8 @@ struct ExtensionSet {
// Convert the set of enabled extension to an LLVM feature list, appending
// them to Features.
void toLLVMFeatureList(std::vector<StringRef> &Features) const;
+
+ void dump() const;
};
// Represents a dependency between two architecture extensions. Later is the
@@ -649,7 +665,16 @@ const ArchInfo *getArchForCpu(StringRef CPU);
// Parser
const ArchInfo *parseArch(StringRef Arch);
+
+// Return the extension which has the given -target-feature name.
+std::optional<ExtensionInfo> targetFeatureToExtension(StringRef TargetFeature);
+
+// Parse a name as defined by the Extension class in tablegen.
std::optional<ExtensionInfo> parseArchExtension(StringRef Extension);
+
+// Parse a name as defined by the FMVInfo class in tablegen.
+std::optional<FMVInfo> parseFMVExtension(StringRef Extension);
+
// Given the name of a CPU or alias, return the correponding CpuInfo.
std::optional<CpuInfo> parseCpu(StringRef Name);
// Used by target parser tests
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 4b2ce0d73949c..850ca08cd02cc 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -19,6 +19,7 @@ include "llvm/Target/Target.td"
// Subtarget features.
//===----------------------------------------------------------------------===//
include "AArch64Features.td"
+include "AArch64FMV.td"
//===----------------------------------------------------------------------===//
// Register File Description
diff --git a/llvm/lib/Target/AArch64/AArch64FMV.td b/llvm/lib/Target/AArch64/AArch64FMV.td
new file mode 100644
index 0000000000000..a19c1d75fff6e
--- /dev/null
+++ b/llvm/lib/Target/AArch64/AArch64FMV.td
@@ -0,0 +1,78 @@
+// Function MultiVersioning (FMV) properties
+
+// Something you can add to target_version or target_clones
+class FMVExtension<string n, string b, string f, int p> {
+ // Name, as spelled in target_version or target_clones. e.g. "memtag"
+ string Name = n;
+
+ // A C++ expression giving the number of the bit in the FMV ABI.
+ // Currently this is given as a value from the enum "CPUFeatures".
+ string Bit = b;
+
+ // SubtargetFeatures to enable for code functions with this FMV feature.
+ string BackendFeatures = f;
+
+ // The FMV priority.
+ int Priority = p;
+}
+
+def : FMVExtension<"aes", "FEAT_AES", "+fp-armv8,+neon", 150>;
+def : FMVExtension<"bf16", "FEAT_BF16", "+bf16", 280>;
+def : FMVExtension<"bti", "FEAT_BTI", "+bti", 510>;
+def : FMVExtension<"crc", "FEAT_CRC", "+crc", 110>;
+def : FMVExtension<"dgh", "FEAT_DGH", "", 260>;
+def : FMVExtension<"dit", "FEAT_DIT", "+dit", 180>;
+def : FMVExtension<"dotprod", "FEAT_DOTPROD", "+dotprod,+fp-armv8,+neon", 104>;
+def : FMVExtension<"dpb", "FEAT_DPB", "+ccpp", 190>;
+def : FMVExtension<"dpb2", "FEAT_DPB2", "+ccpp,+ccdp", 200>;
+def : FMVExtension<"ebf16", "FEAT_EBF16", "+bf16", 290>;
+def : FMVExtension<"f32mm", "FEAT_SVE_F32MM", "+sve,+f32mm,+fullfp16,+fp-armv8,+neon", 350>;
+def : FMVExtension<"f64mm", "FEAT_SVE_F64MM", "+sve,+f64mm,+fullfp16,+fp-armv8,+neon", 360>;
+def : FMVExtension<"fcma", "FEAT_FCMA", "+fp-armv8,+neon,+complxnum", 220>;
+def : FMVExtension<"flagm", "FEAT_FLAGM", "+flagm", 20>;
+def : FMVExtension<"flagm2", "FEAT_FLAGM2", "+flagm,+altnzcv", 30>;
+def : FMVExtension<"fp", "FEAT_FP", "+fp-armv8,+neon", 90>;
+def : FMVExtension<"fp16", "FEAT_FP16", "+fullfp16,+fp-armv8,+neon", 170>;
+def : FMVExtension<"fp16fml", "FEAT_FP16FML", "+fp16fml,+fullfp16,+fp-armv8,+neon", 175>;
+def : FMVExtension<"frintts", "FEAT_FRINTTS", "+fptoint", 250>;
+def : FMVExtension<"i8mm", "FEAT_I8MM", "+i8mm", 270>;
+def : FMVExtension<"jscvt", "FEAT_JSCVT", "+fp-armv8,+neon,+jsconv", 210>;
+def : FMVExtension<"ls64", "FEAT_LS64", "", 520>;
+def : FMVExtension<"ls64_accdata", "FEAT_LS64_ACCDATA", "+ls64", 540>;
+def : FMVExtension<"ls64_v", "FEAT_LS64_V", "", 530>;
+def : FMVExtension<"lse", "FEAT_LSE", "+lse", 80>;
+def : FMVExtension<"memtag", "FEAT_MEMTAG", "", 440>;
+def : FMVExtension<"memtag2", "FEAT_MEMTAG2", "+mte", 450>;
+def : FMVExtension<"memtag3", "FEAT_MEMTAG3", "+mte", 460>;
+def : FMVExtension<"mops", "FEAT_MOPS", "+mops", 650>;
+def : FMVExtension<"pmull", "FEAT_PMULL", "+aes,+fp-armv8,+neon", 160>;
+def : FMVExtension<"predres", "FEAT_PREDRES", "+predres", 480>;
+def : FMVExtension<"rcpc", "FEAT_RCPC", "+rcpc", 230>;
+def : FMVExtension<"rcpc2", "FEAT_RCPC2", "+rcpc", 240>;
+def : FMVExtension<"rcpc3", "FEAT_RCPC3", "+rcpc,+rcpc3", 241>;
+def : FMVExtension<"rdm", "FEAT_RDM", "+rdm,+fp-armv8,+neon", 108>;
+def : FMVExtension<"rng", "FEAT_RNG", "+rand", 10>;
+def : FMVExtension<"rpres", "FEAT_RPRES", "", 300>;
+def : FMVExtension<"sb", "FEAT_SB", "+sb", 470>;
+def : FMVExtension<"sha1", "FEAT_SHA1", "+fp-armv8,+neon", 120>;
+def : FMVExtension<"sha2", "FEAT_SHA2", "+sha2,+fp-armv8,+neon", 130>;
+def : FMVExtension<"sha3", "FEAT_SHA3", "+sha3,+sha2,+fp-armv8,+neon", 140>;
+def : FMVExtension<"simd", "FEAT_SIMD", "+fp-armv8,+neon", 100>;
+def : FMVExtension<"sm4", "FEAT_SM4", "+sm4,+fp-armv8,+neon", 106>;
+def : FMVExtension<"sme", "FEAT_SME", "+sme,+bf16", 430>;
+def : FMVExtension<"sme-f64f64", "FEAT_SME_F64", "+sme,+sme-f64f64,+bf16", 560>;
+def : FMVExtension<"sme-i16i64", "FEAT_SME_I64", "+sme,+sme-i16i64,+bf16", 570>;
+def : FMVExtension<"sme2", "FEAT_SME2", "+sme2,+sme,+bf16", 580>;
+def : FMVExtension<"ssbs", "FEAT_SSBS", "", 490>;
+def : FMVExtension<"ssbs2", "FEAT_SSBS2", "+ssbs", 500>;
+def : FMVExtension<"sve", "FEAT_SVE", "+sve,+fullfp16,+fp-armv8,+neon", 310>;
+def : FMVExtension<"sve-bf16", "FEAT_SVE_BF16", "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 320>;
+def : FMVExtension<"sve-ebf16", "FEAT_SVE_EBF16", "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 330>;
+def : FMVExtension<"sve-i8mm", "FEAT_SVE_I8MM", "+sve,+i8mm,+fullfp16,+fp-armv8,+neon", 340>;
+def : FMVExtension<"sve2", "FEAT_SVE2", "+sve2,+sve,+fullfp16,+fp-armv8,+neon", 370>;
+def : FMVExtension<"sve2-aes", "FEAT_SVE_AES", "+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 380>;
+def : FMVExtension<"sve2-bitperm", "FEAT_SVE_BITPERM", "+sve2,+sve,+sve2-bitperm,+fullfp16,+fp-armv8,+neon", 400>;
+def : FMVExtension<"sve2-pmull128", "FEAT_SVE_PMULL128", "+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 390>;
+def : FMVExtension<"sve2-sha3", "FEAT_SVE_SHA3", "+sve2,+sve,+sve2-sha3,+fullfp16,+fp-armv8,+neon", 410>;
+def : FMVExtension<"sve2-sm4", "FEAT_SVE_SM4", "+sve2,+sve,+sve2-sm4,+fullfp16,+fp-armv8,+neon", 420>;
+def : FMVExtension<"wfxt", "FEAT_WFXT", "+wfxt", 550>;
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index ba0b760ce3d73..acf9656ba9c81 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -11,24 +11,11 @@
// A SubtargetFeature that can be toggled from the command line, and therefore
// has an AEK_* entry in ArmExtKind.
-//
-// If Function MultiVersioning (FMV) properties are left at their defaults
-// (FEAT_INIT, no dependencies, priority 0) it indiates that this extension is
-// not an FMV feature, but can be enabled via the command line (-march, -mcpu,
-// etc).
-//
-// Conversely if the ArchExtKindSpelling is set to AEK_NONE, this indicates
-// that a feature is FMV-only, and can not be selected on the command line.
-// Such extensions should be added via FMVOnlyExtension.
class Extension<
string TargetFeatureName, // String used for -target-feature and -march, unless overridden.
string Spelling, // The XYZ in HasXYZ and AEK_XYZ.
string Desc, // Description.
- list<SubtargetFeature> Implies = [], // List of dependent features.
- // FMV properties
- string _FMVBit = "FEAT_INIT", // FEAT_INIT is repurposed to indicate "not an FMV feature"
- string _FMVDependencies = "",
- int _FMVPriority = 0
+ list<SubtargetFeature> Implies = [] // List of dependent features.
> : SubtargetFeature<TargetFeatureName, "Has" # Spelling, "true", Desc, Implies>
{
string ArchExtKindSpelling = "AEK_" # Spelling; // ArchExtKind enum name.
@@ -42,57 +29,9 @@ class Extension<
// An alias that can be used on the command line, if the extension has one.
// Used for correcting historical names while remaining backwards compatible.
string MArchAlias = "";
-
- // Function MultiVersioning (FMV) properties
-
- // A C++ expression giving the number of the bit in the FMV ABI.
- // Currently this is given as a value from the enum "CPUFeatures".
- // If this is not set, it indicates that this is not an FMV extension.
- string FMVBit = _FMVBit;
-
- // List of features that this feature depends on.
- // FIXME generate this from Implies.
- string FMVDependencies = _FMVDependencies;
-
- // The FMV priority
- int FMVPriority = _FMVPriority;
}
-// Some extensions are available for FMV but can not be controlled via the
-// command line. These entries:
-// - are SubtargetFeatures, so they have (unused) FieldNames on the subtarget
-// e.g. HasFMVOnlyFEAT_XYZ
-// - have incorrect (empty) Implies fields, because the code that handles FMV
-// ignores these dependencies and looks only at FMVDependencies.
-// - have no description.
-//
-// In the generated data structures for extensions (ExtensionInfo), AEK_NONE is
-// used to indicate that a feature is FMV only. Therefore ArchExtKindSpelling is
-// manually overridden here.
-class FMVOnlyExtension<string FMVBit, string Name, string Deps, int Priority>
- : Extension<Name, "FMVOnly"#FMVBit, "", [], FMVBit, Deps, Priority> {
- let ArchExtKindSpelling = "AEK_NONE"; // AEK_NONE indicates FMV-only feature
-}
-def : FMVOnlyExtension<"FEAT_DGH", "dgh", "", 260>;
-def : FMVOnlyExtension<"FEAT_DPB", "dpb", "+ccpp", 190>;
-def : FMVOnlyExtension<"FEAT_DPB2", "dpb2", "+ccpp,+ccdp", 200>;
-def : FMVOnlyExtension<"FEAT_EBF16", "ebf16", "+bf16", 290>;
-def : FMVOnlyExtension<"FEAT_FLAGM2", "flagm2", "+flagm,+altnzcv", 30>;
-def : FMVOnlyExtension<"FEAT_FRINTTS", "frintts", "+fptoint", 250>;
-def : FMVOnlyExtension<"FEAT_LS64_ACCDATA", "ls64_accdata", "+ls64", 540>;
-def : FMVOnlyExtension<"FEAT_LS64_V", "ls64_v", "", 530>;
-def : FMVOnlyExtension<"FEAT_MEMTAG2", "memtag2", "+mte", 450>;
-def : FMVOnlyExtension<"FEAT_MEMTAG3", "memtag3", "+mte", 460>;
-def : FMVOnlyExtension<"FEAT_PMULL", "pmull", "+aes,+fp-armv8,+neon", 160>;
-def : FMVOnlyExtension<"FEAT_RCPC2", "rcpc2", "+rcpc", 240>;
-def : FMVOnlyExtension<"FEAT_RPRES", "rpres", "", 300>;
-def : FMVOnlyExtension<"FEAT_SHA1", "sha1", "+fp-armv8,+neon", 120>;
-def : FMVOnlyExtension<"FEAT_SSBS2", "ssbs2", "+ssbs", 500>;
-def : FMVOnlyExtension<"FEAT_SVE_BF16", "sve-bf16", "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 320>;
-def : FMVOnlyExtension<"FEAT_SVE_EBF16", "sve-ebf16", "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 330>;
-def : FMVOnlyExtension<"FEAT_SVE_I8MM", "sve-i8mm", "+sve,+i8mm,+fullfp16,+fp-armv8,+neon", 340>;
-def : FMVOnlyExtension<"FEAT_SVE_PMULL128", "sve2-pmull128", "+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 390>;
// Each SubtargetFeature which corresponds to an Arm Architecture feature should
@@ -103,33 +42,27 @@ def : FMVOnlyExtension<"FEAT_SVE_PMULL128", "sve2-pmull128", "+sve2,+sve,+sve2-a
let ArchExtKindSpelling = "AEK_FP", MArchName = "fp" in
def FeatureFPARMv8 : Extension<"fp-armv8", "FPARMv8",
- "Enable ARMv8 (FEAT_FP)", [],
- "FEAT_FP", "+fp-armv8,+neon", 90>;
+ "Enable ARMv8 (FEAT_FP)">;
let ArchExtKindSpelling = "AEK_SIMD", MArchName = "simd" in
def FeatureNEON : Extension<"neon", "NEON",
- "Enable Advanced SIMD instructions (FEAT_AdvSIMD)", [FeatureFPARMv8],
- "FEAT_SIMD", "+fp-armv8,+neon", 100>;
+ "Enable Advanced SIMD instructions (FEAT_AdvSIMD)", [FeatureFPARMv8]>;
def FeatureSM4 : Extension<
"sm4", "SM4",
- "Enable SM3 and SM4 support (FEAT_SM4, FEAT_SM3)", [FeatureNEON],
- "FEAT_SM4", "+sm4,+fp-armv8,+neon", 106>;
+ "Enable SM3 and SM4 support (FEAT_SM4, FEAT_SM3)", [FeatureNEON]>;
def FeatureSHA2 : Extension<
"sha2", "SHA2",
- "Enable SHA1 and SHA256 support (FEAT_SHA1, FEAT_SHA256)", [FeatureNEON],
- "FEAT_SHA2", "+sha2,+fp-armv8,+neon", 130>;
+ "Enable SHA1 and SHA256 support (FEAT_SHA1, FEAT_SHA256)", [FeatureNEON]>;
def FeatureSHA3 : Extension<
"sha3", "SHA3",
- "Enable SHA512 and SHA3 support (FEAT_SHA3, FEAT_SHA512)", [FeatureNEON, FeatureSHA2],
- "FEAT_SHA3", "+sha3,+sha2,+fp-armv8,+neon", 140>;
+ "Enable SHA512 and SHA3 support (FEAT_SHA3, FEAT_SHA512)", [FeatureNEON, FeatureSHA2]>;
def FeatureAES : Extension<
"aes", "AES",
- "Enable AES support (FEAT_AES, FEAT_PMULL)", [FeatureNEON],
- "FEAT_AES", "+fp-armv8,+neon", 150>;
+ "Enable AES support (FEAT_AES, FEAT_PMULL)", [FeatureNEON]>;
// Crypto has been split up and any combination is now valid (see the
// crypto definitions above). Also, crypto is now context sensitive:
@@ -139,13 +72,11 @@ def FeatureAES : Extension<
// meaning anymore. We kept the Crypto definition here for backward
// compatibility, and now imply features SHA2 and AES, which was the
// "traditional" meaning of Crypto.
-let FMVDependencies = "+aes,+sha2" in
def FeatureCrypto : Extension<"crypto", "Crypto",
"Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
def FeatureCRC : Extension<"crc", "CRC",
- "Enable ARMv8 CRC-32 checksum instructions (FEAT_CRC32)", [],
- "FEAT_CRC", "+crc", 110>;
+ "Enable ARMv8 CRC-32 checksum instructions (FEAT_CRC32)">;
def FeatureRAS : Extension<"ras", "RAS",
"Enable ARMv8 Reliability, Availability and Serviceability Extensions (FEAT_RAS, FEAT_RASv1p1)">;
@@ -155,8 +86,7 @@ def FeatureRASv2 : Extension<"rasv2", "RASv2",
[FeatureRAS]>;
def FeatureLSE : Extension<"lse", "LSE",
- "Enable ARMv8.1 Large System Extension (LSE) atomic instructions (FEAT_LSE)", [],
- "FEAT_LSE", "+lse", 80>;
+ "Enable ARMv8.1 Large System Extension (LSE) atomic instructions (FEAT_LSE)">;
def FeatureLSE2 : SubtargetFeature<"lse2", "HasLSE2", "true",
"Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules (FEAT_LSE2)">;
@@ -170,8 +100,7 @@ def FeatureFMV : SubtargetFeature<"fmv", "HasFMV", "true",
let MArchAlias = "rdma" in
def FeatureRDM : Extension<"rdm", "RDM",
"Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions (FEAT_RDM)",
- [FeatureNEON],
- "FEAT_RDM", "+rdm,+fp-armv8,+neon", 108>;
+ [FeatureNEON]>;
def FeaturePAN : SubtargetFeature<
"pan", "HasPAN", "true",
@@ -196,12 +125,10 @@ def FeaturePerfMon : Extension<"perfmon", "PerfMon",
let ArchExtKindSpelling = "AEK_FP16", MArchName = "fp16" in
def FeatureFullFP16 : Extension<"fullfp16", "FullFP16",
- "Full FP16 (FEAT_FP16)", [FeatureFPARMv8],
- "FEAT_FP16", "+fullfp16,+fp-armv8,+neon", 170>;
+ "Full FP16 (FEAT_FP16)", [FeatureFPARMv8]>;
def FeatureFP16FML : Extension<"fp16fml", "FP16FML",
- "Enable FP16 FML instructions (FEAT_FHM)", [FeatureFullFP16],
- "FEAT_FP16FML", "+fp16fml,+fullfp16,+fp-armv8,+neon", 175>;
+ "Enable FP16 FML instructions (FEAT_FHM)", [FeatureFullFP16]>;
let ArchExtKindSpelling = "AEK_PROFILE", MArchName = "profile" in
def FeatureSPE : Extension<"spe", "SPE",
@@ -220,13 +147,11 @@ def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP",
"true", "Enable v8.2 data Cache Clean to Point of Persistence (FEAT_DPB)" >;
def FeatureSVE : Extension<"sve", "SVE",
- "Enable Scalable Vector Extension (SVE) instructions (FEAT_SVE)", [FeatureFullFP16],
- "FEAT_SVE", "+sve,+fullfp16,+fp-armv8,+neon", 310>;
+ "Enable Scalable Vector Extension (SVE) instructions (FEAT_SVE)", [FeatureFullFP16]>;
def FeatureFPMR : Extension<"fpmr", "FPMR",
"Enable FPMR Register (FEAT_FPMR)">;
-let FMVDependencies = "+fpmr" in
def FeatureFP8 : Extension<"fp8", "FP8",
"Enable FP8 instructions (FEAT_FP8)">;
@@ -252,35 +177,28 @@ def FeatureUseScalarIncVL : SubtargetFeature<"use-scalar-inc-vl",
"UseScalarIncVL", "true", "Prefer inc/dec over add+cnt">;
def FeatureBF16 : Extension<"bf16", "BF16",
- "Enable BFloat16 Extension (FEAT_BF16)", [],
- "FEAT_BF16", "+bf16", 280>;
+ "Enable BFloat16 Extension (FEAT_BF16)">;
def FeatureNoSVEFPLD1R : SubtargetFeature<"no-sve-fp-ld1r",
"NoSVEFPLD1R", "true", "Avoid using LD1RX instructions for FP">;
def FeatureSVE2 : Extension<"sve2", "SVE2",
"Enable Scalable Vector Extension 2 (SVE2) instructions (FEAT_SVE2)",
- [FeatureSVE, FeatureUseScalarIncVL],
- "FEAT_SVE2", "+sve2,+sve,+fullfp16,+fp-armv8,+neon", 370>;
+ [FeatureSVE, FeatureUseScalarIncVL]>;
def FeatureSVE2AES : Extension<"sve2-aes", "SVE2AES",
"Enable AES SVE2 instructions (FEAT_SVE_AES, FEAT_SVE_PMULL128)",
- [FeatureSVE2, FeatureAES],
- "FEAT_SVE_AES", "+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 380>;
+ [FeatureSVE2, FeatureAES]>;
def FeatureSVE2SM4 : Extension<"sve2-sm4", "SVE2SM4",
- "Enable SM4 SVE2 instructions (FEAT_SVE_SM4)", [FeatureSVE2, FeatureSM4],
- "FEAT_SVE_SM4", "+sve2,+sve,+sve2-sm4,+fullfp16,+fp-armv8,+neon", 420>;
+ "Enable SM4 SVE2 instructions (FEAT_SVE_SM4)", [FeatureSVE2, FeatureSM4]>;
def FeatureSVE2SHA3 : Extension<"sve2-sha3", "SVE2SHA3",
- "Enable SHA3 SVE2 instructions (FEAT_SVE_SHA3)", [FeatureSVE2, FeatureSHA3],
- "FEAT_SVE_SHA3", "+sve2,+sve,+sve2-sha3,+fullfp16,+fp-armv8,+neon", 410>;
+ "Enable SHA3 SVE2 instructions (FEAT_SVE_SHA3)", [FeatureSVE2, FeatureSHA3]>;
def FeatureSVE2BitPerm : Extension<"sve2-bitperm", "SVE2BitPerm",
- "Enable bit permutation SVE2 instructions (FEAT_SVE_BitPerm)", [FeatureSVE2],
- "FEAT_SVE_BITPERM", "+sve2,+sve,+sve2-bitperm,+fullfp16,+fp-armv8,+neon", 400>;
+ "Enable bit permutation SVE2 instructions (FEAT_SVE_BitPerm)", [FeatureSVE2]>;
-let FMVDependencies = "+sve2p1,+sve2,+sve,+fullfp16,+fp-armv8,+neon" in
def FeatureSVE2p1: Extension<"sve2p1", "SVE2p1",
"Enable Scalable Vector Extension 2.1 instructions", [FeatureSVE2]>;
@@ -417,8 +335,7 @@ def FeatureForce32BitJumpTables
"Force jump table entries to be 32-bits wide except at MinSize">;
def FeatureRCPC : Extension<"rcpc", "RCPC",
- "Enable support for RCPC extension (FEAT_LRCPC)", [],
- "FEAT_RCPC", "+rcpc", 230>;
+ "Enable support for RCPC extension (FEAT_LRCPC)">;
def FeatureUseRSqrt : SubtargetFeature<
"use-reciprocal-square-root", "UseRSqrt", "true",
@@ -426,8 +343,7 @@ def FeatureUseRSqrt : SubtargetFeature<
def FeatureDotProd : Extension<
"dotprod", "DotProd",
- "Enable dot product support (FEAT_DotProd)", [FeatureNEON],
- "FEAT_DOTPROD", "+dotprod,+fp-armv8,+neon", 104>;
+ "Enable dot product support (FEAT_DotProd)", [FeatureNEON]>;
def FeaturePAuth : Extension<
"pauth", "PAuth",
@@ -437,8 +353,7 @@ let ArchExtKindSpelling = "AEK_JSCVT", MArchName = "jscvt" in
def FeatureJS : Extension<
"jsconv", "JS",
"Enable v8.3-A JavaScript FP conversion instructions (FEAT_JSCVT)",
- [FeatureFPARMv8],
- "FEAT_JSCVT", "+fp-armv8,+neon,+jsconv", 210>;
+ [FeatureFPARMv8]>;
def FeatureCCIDX : SubtargetFeature<
"ccidx", "HasCCIDX", "true",
@@ -448,8 +363,7 @@ let ArchExtKindSpelling = "AEK_FCMA", MArchName = "fcma" in
def FeatureComplxNum : Extension<
"complxnum", "ComplxNum",
"Enable v8.3-A Floating-point complex number support (FEAT_FCMA)",
- [FeatureNEON],
- "FEAT_FCMA", "+fp-armv8,+neon,+complxnum", 220>;
+ [FeatureNEON]>;
def FeatureNV : SubtargetFeature<
"nv", "HasNV", "true",
@@ -461,8 +375,7 @@ def FeatureMPAM : SubtargetFeature<
def FeatureDIT : Extension<
"dit", "DIT",
- "Enable v8.4-A Data Independent Timing instructions (FEAT_DIT)", [],
- "FEAT_DIT", "+dit", 180>;
+ "Enable v8.4-A Data Independent Timing instructions (FEAT_DIT)">;
def FeatureTRACEV8_4 : SubtargetFeature<
"tracev8.4", "HasTRACEV8_4", "true",
@@ -487,8 +400,7 @@ def FeatureTLB_RMI : SubtargetFeature<
def FeatureFlagM : Extension<
"flagm", "FlagM",
- "Enable v8.4-A Flag Manipulation Instructions (FEAT_FlagM)", [],
- "FEAT_FLAGM", "+flagm", 20>;
+ "Enable v8.4-A Flag Manipulation Instructions (FEAT_FlagM)">;
// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset
def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true",
@@ -536,41 +448,34 @@ def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict",
"true", "Enable architectural speculation restriction (FEAT_CSV2_2)">;
def FeatureSB : Extension<"sb", "SB",
- "Enable v8.5 Speculation Barrier (FEAT_SB)", [],
- "FEAT_SB", "+sb", 470>;
+ "Enable v8.5 Speculation Barrier (FEAT_SB)">;
def FeatureSSBS : Extension<"ssbs", "SSBS",
- "Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2)", [],
- "FEAT_SSBS", "", 490>;
+ "Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2)">;
def FeaturePredRes : Extension<"predres", "PredRes",
- "Enable v8.5a execution and data prediction invalidation instructions (FEAT_SPECRES)", [],
- "FEAT_PREDRES", "+predres", 480>;
+ "Enable v8.5a execution and data prediction invalidation instructions (FEAT_SPECRES)">;
-def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "CCDP", "true",
+def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP", "true",
"Enable v8.5 Cache Clean to Point of Deep Persistence (FEAT_DPB2)" >;
-let ArchExtKindSpelling = "AEK_NONE" in
-def FeatureBranchTargetId : Extension<"bti", "BTI",
- "Enable Branch Target Identification (FEAT_BTI)", [],
- "FEAT_BTI", "+bti", 510>;
+def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI", "true",
+ "Enable Branch Target Identification (FEAT_BTI)">;
let ArchExtKindSpelling = "AEK_RAND", MArchName = "rng" in
def FeatureRandGen : Extension<"rand", "RandGen",
- "Enable Random Number generation instructions (FEAT_RNG)", [],
- "FEAT_RNG", "+rand", 10>;
+ "Enable Random Number generation instructions (FEAT_RNG)">;
// NOTE: "memtag" means FEAT_MTE + FEAT_MTE2 for -march or
// __attribute((target(...))), but only FEAT_MTE for FMV.
let MArchName = "memtag" in
def FeatureMTE : Extension<"mte", "MTE",
- "Enable Memory Tagging Extension (FEAT_MTE, FEAT_MTE2)", [],
- "FEAT_MEMTAG", "", 440>;
+ "Enable Memory Tagging Extension (FEAT_MTE, FEAT_MTE2)">;
-def FeatureTRBE : SubtargetFeature<"trbe", "TRBE", "true",
+def FeatureTRBE : SubtargetFeature<"trbe", "HasTRBE", "true",
"Enable Trace Buffer Extension (FEAT_TRBE)">;
-def FeatureETE : SubtargetFeature<"ete", "ETE", "true",
+def FeatureETE : SubtargetFeature<"ete", "HasETE", "true",
"Enable Embedded Trace Extension (FEAT_ETE)",
[FeatureTRBE]>;
@@ -584,39 +489,33 @@ def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
let ArchExtKindSpelling = "AEK_I8MM" in
def FeatureMatMulInt8 : Extension<"i8mm", "MatMulInt8",
- "Enable Matrix Multiply Int8 Extension (FEAT_I8MM)", [],
- "FEAT_I8MM", "+i8mm", 270>;
+ "Enable Matrix Multiply Int8 Extension (FEAT_I8MM)">;
let ArchExtKindSpelling = "AEK_F32MM" in
def FeatureMatMulFP32 : Extension<"f32mm", "MatMulFP32",
- "Enable Matrix Multiply FP32 Extension (FEAT_F32MM)", [FeatureSVE],
- "FEAT_SVE_F32MM", "+sve,+f32mm,+fullfp16,+fp-armv8,+neon", 350>;
+ "Enable Matrix Multiply FP32 Extension (FEAT_F32MM)", [FeatureSVE]>;
let ArchExtKindSpelling = "AEK_F64MM" in
def FeatureMatMulFP64 : Extension<"f64mm", "MatMulFP64",
- "Enable Matrix Multiply FP64 Extension (FEAT_F64MM)", [FeatureSVE],
- "FEAT_SVE_F64MM", "+sve,+f64mm,+fullfp16,+fp-armv8,+neon", 360>;
+ "Enable Matrix Multiply FP64 Extension (FEAT_F64MM)", [FeatureSVE]>;
def FeatureXS : SubtargetFeature<"xs", "HasXS",
"true", "Enable Armv8.7-A limited-TLB-maintenance instruction (FEAT_XS)">;
-def FeatureWFxT : Extension<"wfxt", "WFxT",
- "Enable Armv8.7-A WFET and WFIT instruction (FEAT_WFxT)", [],
- "FEAT_WFXT", "+wfxt", 550>;
+def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT", "true",
+ "Enable Armv8.7-A WFET and WFIT instruction (FEAT_WFxT)">;
def FeatureHCX : SubtargetFeature<
"hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register (FEAT_HCX)">;
def FeatureLS64 : Extension<"ls64", "LS64",
- "Enable Armv8.7-A LD64B/ST64B Accelerator Extension (FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA)", [],
- "FEAT_LS64", "", 520>;
+ "Enable Armv8.7-A LD64B/ST64B Accelerator Extension (FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA)">;
def FeatureHBC : Extension<"hbc", "HBC",
"Enable Armv8.8-A Hinted Conditional Branches Extension (FEAT_HBC)">;
def FeatureMOPS : Extension<"mops", "MOPS",
- "Enable Armv8.8-A memcpy and memset acceleration instructions (FEAT_MOPS)", [],
- "FEAT_MOPS", "+mops", 650>;
+ "Enable Armv8.8-A memcpy and memset acceleration instructions (FEAT_MOPS)">;
def FeatureNMI : SubtargetFeature<"nmi", "HasNMI",
"true", "Enable Armv8.8-A Non-maskable Interrupts (FEAT_NMI, FEAT_GICv3_NMI)">;
@@ -638,67 +537,56 @@ def FeatureRME : SubtargetFeature<"rme", "HasRME",
"true", "Enable Realm Management Extension (FEAT_RME)">;
def FeatureSME : Extension<"sme", "SME",
- "Enable Scalable Matrix Extension (SME) (FEAT_SME)", [FeatureBF16, FeatureUseScalarIncVL],
- "FEAT_SME", "+sme,+bf16", 430>;
+ "Enable Scalable Matrix Extension (SME) (FEAT_SME)", [FeatureBF16, FeatureUseScalarIncVL]>;
def FeatureSMEF64F64 : Extension<"sme-f64f64", "SMEF64F64",
- "Enable Scalable Matrix Extension (SME) F64F64 instructions (FEAT_SME_F64F64)", [FeatureSME],
- "FEAT_SME_F64", "+sme,+sme-f64f64,+bf16", 560>;
+ "Enable Scalable Matrix Extension (SME) F64F64 instructions (FEAT_SME_F64F64)", [FeatureSME]>;
def FeatureSMEI16I64 : Extension<"sme-i16i64", "SMEI16I64",
- "Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)", [FeatureSME],
- "FEAT_SME_I64", "+sme,+sme-i16i64,+bf16", 570>;
+ "Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)", [FeatureSME]>;
def FeatureSMEFA64 : Extension<"sme-fa64", "SMEFA64",
"Enable the full A64 instruction set in streaming SVE mode (FEAT_SME_FA64)", [FeatureSME, FeatureSVE2]>;
def FeatureSME2 : Extension<"sme2", "SME2",
- "Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME],
- "FEAT_SME2", "+sme2,+sme,+bf16", 580>;
+ "Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME]>;
-let FMVDependencies = "+sme2,+sme-f16f16" in
def FeatureSMEF16F16 : Extension<"sme-f16f16", "SMEF16F16",
"Enable SME non-widening Float16 instructions (FEAT_SME_F16F16)", [FeatureSME2]>;
-let FMVDependencies = "+sme2p1,+sme2,+sme,+bf16" in
def FeatureSME2p1 : Extension<"sme2p1", "SME2p1",
"Enable Scalable Matrix Extension 2.1 (FEAT_SME2p1) instructions", [FeatureSME2]>;
def FeatureFAMINMAX: Extension<"faminmax", "FAMINMAX",
"Enable FAMIN and FAMAX instructions (FEAT_FAMINMAX)">;
-let FMVDependencies = "+fpmr" in
def FeatureFP8FMA : Extension<"fp8fma", "FP8FMA",
"Enable fp8 multiply-add instructions (FEAT_FP8FMA)">;
-let FMVDependencies = "+sme2" in
def FeatureSSVE_FP8FMA : Extension<"ssve-fp8fma", "SSVE_FP8FMA",
"Enable SVE2 fp8 multiply-add instructions (FEAT_SSVE_FP8FMA)", [FeatureSME2]>;
def FeatureFP8DOT2: Extension<"fp8dot2", "FP8DOT2",
"Enable fp8 2-way dot instructions (FEAT_FP8DOT2)">;
-let FMVDependencies = "+sme2" in
def FeatureSSVE_FP8DOT2 : Extension<"ssve-fp8dot2", "SSVE_FP8DOT2",
"Enable SVE2 fp8 2-way dot product instructions (FEAT_SSVE_FP8DOT2)", [FeatureSME2]>;
def FeatureFP8DOT4: Extension<"fp8dot4", "FP8DOT4",
"Enable fp8 4-way dot instructions (FEAT_FP8DOT4)">;
-let FMVDependencies = "+sme2" in
def FeatureSSVE_FP8DOT4 : Extension<"ssve-fp8dot4", "SSVE_FP8DOT4",
"Enable SVE2 fp8 4-way dot product instructions (FEAT_SSVE_FP8DOT4)", [FeatureSME2]>;
+
def FeatureLUT: Extension<"lut", "LUT",
"Enable Lookup Table instructions (FEAT_LUT)">;
def FeatureSME_LUTv2 : Extension<"sme-lutv2", "SME_LUTv2",
"Enable Scalable Matrix Extension (SME) LUTv2 instructions (FEAT_SME_LUTv2)">;
-let FMVDependencies = "+fp8,+sme2" in
def FeatureSMEF8F16 : Extension<"sme-f8f16", "SMEF8F16",
"Enable Scalable Matrix Extension (SME) F8F16 instructions(FEAT_SME_F8F16)", [FeatureSME2, FeatureFP8]>;
-let FMVDependencies = "+sme2,+fp8" in
def FeatureSMEF8F32 : Extension<"sme-f8f32", "SMEF8F32",
"Enable Scalable Matrix Extension (SME) F8F32 instructions (FEAT_SME_F8F32)", [FeatureSME2, FeatureFP8]>;
@@ -748,8 +636,7 @@ def FeatureITE : Extension<"ite", "ITE",
def FeatureRCPC3 : Extension<"rcpc3", "RCPC3",
"Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set (FEAT_LRCPC3)",
- [FeatureRCPC_IMMO],
- "FEAT_RCPC3", "+rcpc,+rcpc3", 241>;
+ [FeatureRCPC_IMMO]>;
def FeatureTHE : Extension<"the", "THE",
"Enable Armv8.9-A Translation Hardening Extension (FEAT_THE)">;
@@ -918,4 +805,4 @@ def FeatureHardenSlsNoComdat : SubtargetFeature<"harden-sls-nocomdat",
// Only intended to be used by disassemblers.
def FeatureAll
- : SubtargetFeature<"all", "IsAll", "true", "Enable all instructions", []>;
+ : SubtargetFeature<"all", "IsAll", "true", "Enable all instructions">;
diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp b/llvm/lib/TargetParser/AArch64TargetParser.cpp
index c10b4be4eded9..9a69b520a0b5e 100644
--- a/llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -23,6 +23,9 @@
using namespace llvm;
+#define EMIT_FMV_INFO
+#include "llvm/TargetParser/AArch64TargetParserDef.inc"
+
static unsigned checkArchVersion(llvm::StringRef Arch) {
if (Arch.size() >= 2 && Arch[0] == 'v' && std::isdigit(Arch[1]))
return (Arch[1] - 48);
@@ -50,8 +53,8 @@ std::optional<AArch64::ArchInfo> AArch64::ArchInfo::findBySubArch(StringRef SubA
uint64_t AArch64::getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs) {
uint64_t FeaturesMask = 0;
for (const StringRef &FeatureStr : FeatureStrs) {
- if (auto Ext = parseArchExtension(FeatureStr))
- FeaturesMask |= (1ULL << Ext->CPUFeature);
+ if (auto Ext = parseFMVExtension(FeatureStr))
+ FeaturesMask |= (1ULL << Ext->Bit);
}
return FeaturesMask;
}
@@ -79,7 +82,7 @@ StringRef AArch64::getArchExtFeature(StringRef ArchExt) {
StringRef ArchExtBase = IsNegated ? ArchExt.drop_front(2) : ArchExt;
if (auto AE = parseArchExtension(ArchExtBase)) {
- // Note: the returned string can be empty.
+ assert(!(AE.has_value() && AE->NegFeature.empty()));
return IsNegated ? AE->NegFeature : AE->Feature;
}
@@ -113,6 +116,15 @@ const AArch64::ArchInfo *AArch64::parseArch(StringRef Arch) {
return {};
}
+std::optional<AArch64::ExtensionInfo>
+AArch64::targetFeatureToExtension(StringRef TargetFeature) {
+ for (const auto &E : Extensions) {
+ if (TargetFeature == E.Feature.substr(1))
+ return E;
+ }
+ return {};
+}
+
std::optional<AArch64::ExtensionInfo>
AArch64::parseArchExtension(StringRef ArchExt) {
for (const auto &A : Extensions) {
@@ -122,6 +134,19 @@ AArch64::parseArchExtension(StringRef ArchExt) {
return {};
}
+std::optional<AArch64::FMVInfo>
+AArch64::parseFMVExtension(StringRef FMVExt) {
+ // FIXME introduce general alias functionality, or remove this exception.
+ if (FMVExt == "rdma")
+ FMVExt = "rdm";
+
+ for (const auto &I : getFMVInfo()) {
+ if (FMVExt == I.Name)
+ return I;
+ }
+ return {};
+}
+
std::optional<AArch64::CpuInfo> AArch64::parseCpu(StringRef Name) {
// Resolve aliases first.
Name = resolveCPUAlias(Name);
@@ -234,6 +259,14 @@ void AArch64::ExtensionSet::toLLVMFeatureList(
}
}
+void AArch64::ExtensionSet::dump() const {
+ std::vector<StringRef> Features;
+ toLLVMFeatureList(Features);
+ for (StringRef F : Features)
+ llvm::outs() << F << " ";
+ llvm::outs() << "\n";
+}
+
void AArch64::ExtensionSet::addCPUDefaults(const CpuInfo &CPU) {
LLVM_DEBUG(llvm::dbgs() << "addCPUDefaults(" << CPU.Name << ")\n");
BaseArch = &CPU.Arch;
diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
index b79458529623f..dd4f929f05044 100644
--- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
@@ -97,25 +97,37 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) {
else
OS << ", \"" << Alias << "\"";
OS << ", AArch64::" << AEK;
- if (AEK == "AEK_NONE") {
- // HACK: don't emit posfeat/negfeat strings for FMVOnlyExtensions.
- OS << ", {}, {}";
- } else {
- OS << ", \"+" << Rec->getValueAsString("Name") << "\""; // posfeature
- OS << ", \"-" << Rec->getValueAsString("Name") << "\""; // negfeature
- }
- OS << ", " << Rec->getValueAsString("FMVBit");
- OS << ", \"" << Rec->getValueAsString("FMVDependencies") << "\"";
- OS << ", " << (uint64_t)Rec->getValueAsInt("FMVPriority");
+ OS << ", \"+" << Rec->getValueAsString("Name") << "\""; // posfeature
+ OS << ", \"-" << Rec->getValueAsString("Name") << "\""; // negfeature
OS << "},\n";
};
- OS << " {\"none\", {}, AArch64::AEK_NONE, {}, {}, FEAT_INIT, \"\", "
- "ExtensionInfo::MaxFMVPriority},\n";
+ OS << " {\"none\", {}, AArch64::AEK_NONE, {}, {} },\n";
OS << "};\n"
<< "#undef EMIT_EXTENSIONS\n"
<< "#endif // EMIT_EXTENSIONS\n"
<< "\n";
+ // Emit FMV information
+ auto FMVExts = RK.getAllDerivedDefinitionsIfDefined("FMVExtension");
+ OS << "#ifdef EMIT_FMV_INFO\n"
+ << "const std::vector<llvm::AArch64::FMVInfo>& llvm::AArch64::getFMVInfo() {\n"
+ << " static std::vector<FMVInfo> I;\n"
+ << " if(I.size()) return I;\n"
+ << " I.reserve(" << FMVExts.size() << ");\n";
+ for (const Record *Rec : FMVExts) {
+ OS << " I.emplace_back(";
+ OS << "\"" << Rec->getValueAsString("Name") << "\"";
+ OS << ", " << Rec->getValueAsString("Bit");
+ OS << ", \"" << Rec->getValueAsString("BackendFeatures") << "\"";
+ OS << ", " << (uint64_t)Rec->getValueAsInt("Priority");
+ OS << ");\n";
+ };
+ OS << " return I;\n"
+ << "}\n"
+ << "#undef EMIT_FMV_INFO\n"
+ << "#endif // EMIT_FMV_INFO\n"
+ << "\n";
+
// Emit architecture information
OS << "#ifdef EMIT_ARCHITECTURES\n";
>From 4b5ca98fdee624eda0d6f8a11843f69ea80e2e92 Mon Sep 17 00:00:00 2001
From: Tomas Matheson <tomas.matheson at arm.com>
Date: Tue, 28 May 2024 15:04:49 +0100
Subject: [PATCH 2/7] remove filterFunctionTargetVersionAttrs
---
clang/lib/AST/ASTContext.cpp | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index bbf72b1440e91..8a8b56710fda8 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -13675,16 +13675,6 @@ GetFMVBackendFeaturesFor(const llvm::SmallVector<StringRef, 8> FMVFeatStrings,
BackendFeats.push_back(F.str());
}
-std::vector<std::string> ASTContext::filterFunctionTargetVersionAttrs(
- const TargetVersionAttr *TV) const {
- assert(TV != nullptr);
- llvm::SmallVector<StringRef, 8> Feats;
- std::vector<std::string> ResFeats;
- TV->getFeatures(Feats);
- GetFMVBackendFeaturesFor(Feats, ResFeats);
- return ResFeats;
-}
-
ParsedTargetAttr
ASTContext::filterFunctionTargetAttrs(const TargetAttr *TD) const {
assert(TD != nullptr);
>From 273dc66a688e3c52d0a67eaab10bcf5c2f22351c Mon Sep 17 00:00:00 2001
From: Tomas Matheson <tomas.matheson at arm.com>
Date: Wed, 29 May 2024 15:44:51 +0100
Subject: [PATCH 3/7] fix one bug
---
clang/lib/AST/ASTContext.cpp | 22 +++++++++++-----------
clang/lib/Basic/Targets/AArch64.cpp | 1 -
2 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 8a8b56710fda8..ae25d9ffc389c 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -13666,13 +13666,14 @@ QualType ASTContext::getCorrespondingSignedFixedPointType(QualType Ty) const {
}
// Given a list of FMV features, add each of their backend features to the list.
-static void
-GetFMVBackendFeaturesFor(const llvm::SmallVector<StringRef, 8> FMVFeatStrings,
- std::vector<std::string>& BackendFeats) {
+static std::vector<std::string> GetFMVBackendFeaturesFor(
+ const llvm::SmallVectorImpl<StringRef> &FMVFeatStrings) {
+ std::vector<std::string> BackendFeats;
for (auto &F : FMVFeatStrings)
if (auto FMVExt = llvm::AArch64::parseFMVExtension(F))
for (auto F : FMVExt->getImpliedFeatures())
BackendFeats.push_back(F.str());
+ return BackendFeats;
}
ParsedTargetAttr
@@ -13733,9 +13734,9 @@ void ASTContext::getFunctionFeatureMap(llvm::StringMap<bool> &FeatureMap,
} else if (const auto *TC = FD->getAttr<TargetClonesAttr>()) {
std::vector<std::string> Features;
if (Target->getTriple().isAArch64()) {
- llvm::SmallVector<StringRef, 8> Feats;
- TC->getFeatures(Feats, GD.getMultiVersionIndex());
- GetFMVBackendFeaturesFor(Feats, Features);
+ llvm::SmallVector<StringRef, 8> AttrExtensions;
+ TC->getFeatures(AttrExtensions, GD.getMultiVersionIndex());
+ Features = GetFMVBackendFeaturesFor(AttrExtensions);
// Combine with the features from the Target, not expanded
Features.insert(Features.begin(),
@@ -13750,11 +13751,10 @@ void ASTContext::getFunctionFeatureMap(llvm::StringMap<bool> &FeatureMap,
}
Target->initFeatureMap(FeatureMap, getDiagnostics(), TargetCPU, Features);
} else if (const auto *TV = FD->getAttr<TargetVersionAttr>()) {
- llvm::SmallVector<StringRef, 8> Feats;
- TV->getFeatures(Feats);
- std::vector<std::string> Features;
- GetFMVBackendFeaturesFor(Feats, Features);
- Feats.insert(Feats.begin(),
+ llvm::SmallVector<StringRef, 8> AttrExtensions;
+ TV->getFeatures(AttrExtensions);
+ auto Features = GetFMVBackendFeaturesFor(AttrExtensions);
+ Features.insert(Features.begin(),
Target->getTargetOpts().FeaturesAsWritten.begin(),
Target->getTargetOpts().FeaturesAsWritten.end());
Target->initFeatureMap(FeatureMap, getDiagnostics(), TargetCPU, Features);
diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
index 9077019affd35..7c191bc7425b0 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -1073,7 +1073,6 @@ bool AArch64TargetInfo::initFeatureMap(
}
if(F == "+sve") {
- UpdatedFeaturesVec.emplace_back("+sve");
UpdatedFeaturesVec.emplace_back("+fullfp16");
UpdatedFeaturesVec.emplace_back("+neon");
UpdatedFeaturesVec.emplace_back("+fp-armv8");
>From 66b4dcd6d074c700346b405c48c7ff608122ae8d Mon Sep 17 00:00:00 2001
From: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: Fri, 14 Jun 2024 08:46:12 +0100
Subject: [PATCH 4/7] Reland "[AArch64] Decouple feature dependency expansion.
(#94279)"
This is the second attempt. We should be inserting the Driver
features in front of the features of a parsed target attribute
to avoid errors like the following:
```
% cat neon.c
__attribute__((target("arch=armv8-a")))
uint64x2_t foo(uint64x2_t a, uint64x2_t b) { return veorq_u64(a, b); }
% clang --target=aarch64-linux-gnu -c neon.c
error: always_inline function 'veorq_u64' requires target feature
'outline-atomics', but would be inlined into function 'foo'
that is compiled without support for 'outline-atomics'
```
---
clang/include/clang/AST/ASTContext.h | 3 -
clang/lib/AST/ASTContext.cpp | 59 +++++-----
clang/lib/AST/CMakeLists.txt | 2 +
clang/lib/Basic/Targets/AArch64.cpp | 105 ++++++-----------
clang/lib/Basic/Targets/AArch64.h | 4 -
.../CodeGen/aarch64-cpu-supports-target.c | 4 +-
.../aarch64-sme-attrs.cpp | 2 +-
clang/test/CodeGen/aarch64-targetattr.c | 48 ++++----
clang/test/CodeGen/attr-target-version.c | 46 ++++----
clang/test/Sema/aarch64-neon-target.c | 4 +-
.../llvm/TargetParser/AArch64TargetParser.h | 107 +++++++++++-------
llvm/lib/TargetParser/AArch64TargetParser.cpp | 51 ++++++---
12 files changed, 213 insertions(+), 222 deletions(-)
diff --git a/clang/include/clang/AST/ASTContext.h b/clang/include/clang/AST/ASTContext.h
index 53ece996769a8..f1f20fca477a4 100644
--- a/clang/include/clang/AST/ASTContext.h
+++ b/clang/include/clang/AST/ASTContext.h
@@ -3210,9 +3210,6 @@ class ASTContext : public RefCountedBase<ASTContext> {
/// valid feature names.
ParsedTargetAttr filterFunctionTargetAttrs(const TargetAttr *TD) const;
- std::vector<std::string>
- filterFunctionTargetVersionAttrs(const TargetVersionAttr *TV) const;
-
void getFunctionFeatureMap(llvm::StringMap<bool> &FeatureMap,
const FunctionDecl *) const;
void getFunctionFeatureMap(llvm::StringMap<bool> &FeatureMap,
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 34aa399fda2f8..aa22825602a40 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -87,6 +87,7 @@
#include "llvm/Support/MD5.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/TargetParser/AArch64TargetParser.h"
#include "llvm/TargetParser/Triple.h"
#include <algorithm>
#include <cassert>
@@ -13676,17 +13677,20 @@ QualType ASTContext::getCorrespondingSignedFixedPointType(QualType Ty) const {
}
}
-std::vector<std::string> ASTContext::filterFunctionTargetVersionAttrs(
- const TargetVersionAttr *TV) const {
- assert(TV != nullptr);
- llvm::SmallVector<StringRef, 8> Feats;
- std::vector<std::string> ResFeats;
- TV->getFeatures(Feats);
- for (auto &Feature : Feats)
- if (Target->validateCpuSupports(Feature.str()))
- // Use '?' to mark features that came from TargetVersion.
- ResFeats.push_back("?" + Feature.str());
- return ResFeats;
+// Given a list of FMV features, return a concatenated list of the
+// corresponding backend features (which may contain duplicates).
+static std::vector<std::string> getFMVBackendFeaturesFor(
+ const llvm::SmallVectorImpl<StringRef> &FMVFeatStrings) {
+ std::vector<std::string> BackendFeats;
+ for (StringRef F : FMVFeatStrings) {
+ if (auto FMVExt = llvm::AArch64::parseArchExtension(F)) {
+ SmallVector<StringRef, 8> Feats;
+ FMVExt->DependentFeatures.split(Feats, ',', -1, false);
+ for (StringRef F : Feats)
+ BackendFeats.push_back(F.str());
+ }
+ }
+ return BackendFeats;
}
ParsedTargetAttr
@@ -13721,10 +13725,12 @@ void ASTContext::getFunctionFeatureMap(llvm::StringMap<bool> &FeatureMap,
// Make a copy of the features as passed on the command line into the
// beginning of the additional features from the function to override.
- ParsedAttr.Features.insert(
- ParsedAttr.Features.begin(),
- Target->getTargetOpts().FeaturesAsWritten.begin(),
- Target->getTargetOpts().FeaturesAsWritten.end());
+ // AArch64 handles command line option features in parseTargetAttr().
+ if (!Target->getTriple().isAArch64())
+ ParsedAttr.Features.insert(
+ ParsedAttr.Features.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.end());
if (ParsedAttr.CPU != "" && Target->isValidCPUName(ParsedAttr.CPU))
TargetCPU = ParsedAttr.CPU;
@@ -13745,32 +13751,31 @@ void ASTContext::getFunctionFeatureMap(llvm::StringMap<bool> &FeatureMap,
Target->getTargetOpts().FeaturesAsWritten.end());
Target->initFeatureMap(FeatureMap, getDiagnostics(), TargetCPU, Features);
} else if (const auto *TC = FD->getAttr<TargetClonesAttr>()) {
- std::vector<std::string> Features;
if (Target->getTriple().isAArch64()) {
- // TargetClones for AArch64
llvm::SmallVector<StringRef, 8> Feats;
TC->getFeatures(Feats, GD.getMultiVersionIndex());
- for (StringRef Feat : Feats)
- if (Target->validateCpuSupports(Feat.str()))
- // Use '?' to mark features that came from AArch64 TargetClones.
- Features.push_back("?" + Feat.str());
+ std::vector<std::string> Features = getFMVBackendFeaturesFor(Feats);
Features.insert(Features.begin(),
Target->getTargetOpts().FeaturesAsWritten.begin(),
Target->getTargetOpts().FeaturesAsWritten.end());
+ Target->initFeatureMap(FeatureMap, getDiagnostics(), TargetCPU, Features);
} else {
+ std::vector<std::string> Features;
StringRef VersionStr = TC->getFeatureStr(GD.getMultiVersionIndex());
if (VersionStr.starts_with("arch="))
TargetCPU = VersionStr.drop_front(sizeof("arch=") - 1);
else if (VersionStr != "default")
Features.push_back((StringRef{"+"} + VersionStr).str());
+ Target->initFeatureMap(FeatureMap, getDiagnostics(), TargetCPU, Features);
}
- Target->initFeatureMap(FeatureMap, getDiagnostics(), TargetCPU, Features);
} else if (const auto *TV = FD->getAttr<TargetVersionAttr>()) {
- std::vector<std::string> Feats = filterFunctionTargetVersionAttrs(TV);
- Feats.insert(Feats.begin(),
- Target->getTargetOpts().FeaturesAsWritten.begin(),
- Target->getTargetOpts().FeaturesAsWritten.end());
- Target->initFeatureMap(FeatureMap, getDiagnostics(), TargetCPU, Feats);
+ llvm::SmallVector<StringRef, 8> Feats;
+ TV->getFeatures(Feats);
+ std::vector<std::string> Features = getFMVBackendFeaturesFor(Feats);
+ Features.insert(Features.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.end());
+ Target->initFeatureMap(FeatureMap, getDiagnostics(), TargetCPU, Features);
} else {
FeatureMap = Target->getTargetOpts().FeatureMap;
}
diff --git a/clang/lib/AST/CMakeLists.txt b/clang/lib/AST/CMakeLists.txt
index a5d3dacfc1a84..0328666d59b1f 100644
--- a/clang/lib/AST/CMakeLists.txt
+++ b/clang/lib/AST/CMakeLists.txt
@@ -139,4 +139,6 @@ add_clang_library(clangAST
omp_gen
ClangDriverOptions
intrinsics_gen
+ # These generated headers are included transitively.
+ AArch64TargetParserTableGen
)
diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
index 08d13c41a4857..6fba5fff7bcc1 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -1052,57 +1052,18 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
return true;
}
-bool AArch64TargetInfo::initFeatureMap(
- llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
- const std::vector<std::string> &FeaturesVec) const {
- std::vector<std::string> UpdatedFeaturesVec;
- // Parse the CPU and add any implied features.
- std::optional<llvm::AArch64::CpuInfo> CpuInfo = llvm::AArch64::parseCpu(CPU);
- if (CpuInfo) {
- auto Exts = CpuInfo->getImpliedExtensions();
- std::vector<StringRef> CPUFeats;
- llvm::AArch64::getExtensionFeatures(Exts, CPUFeats);
- for (auto F : CPUFeats) {
- assert((F[0] == '+' || F[0] == '-') && "Expected +/- in target feature!");
- UpdatedFeaturesVec.push_back(F.str());
- }
- }
-
- // Process target and dependent features. This is done in two loops collecting
- // them into UpdatedFeaturesVec: first to add dependent '+'features, second to
- // add target '+/-'features that can later disable some of features added on
- // the first loop. Function Multi Versioning features begin with '?'.
- for (const auto &Feature : FeaturesVec)
- if (((Feature[0] == '?' || Feature[0] == '+')) &&
- AArch64TargetInfo::doesFeatureAffectCodeGen(Feature.substr(1))) {
- StringRef DepFeatures =
- AArch64TargetInfo::getFeatureDependencies(Feature.substr(1));
- SmallVector<StringRef, 1> AttrFeatures;
- DepFeatures.split(AttrFeatures, ",");
- for (auto F : AttrFeatures)
- UpdatedFeaturesVec.push_back(F.str());
- }
- for (const auto &Feature : FeaturesVec)
- if (Feature[0] != '?') {
- std::string UpdatedFeature = Feature;
- if (Feature[0] == '+') {
- std::optional<llvm::AArch64::ExtensionInfo> Extension =
- llvm::AArch64::parseArchExtension(Feature.substr(1));
- if (Extension)
- UpdatedFeature = Extension->Feature.str();
- }
- UpdatedFeaturesVec.push_back(UpdatedFeature);
- }
-
- return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec);
-}
-
// Parse AArch64 Target attributes, which are a comma separated list of:
// "arch=<arch>" - parsed to features as per -march=..
// "cpu=<cpu>" - parsed to features as per -mcpu=.., with CPU set to <cpu>
// "tune=<cpu>" - TuneCPU set to <cpu>
// "feature", "no-feature" - Add (or remove) feature.
// "+feature", "+nofeature" - Add (or remove) feature.
+//
+// A feature may correspond to an Extension (anything with a corresponding
+// AEK_), in which case an ExtensionSet is used to parse it and expand its
+// dependencies. Otherwise the feature is passed through (e.g. +v8.1a,
+// +outline-atomics, -fmv, etc). Features coming from the command line are
+// already parsed, therefore their dependencies do not need expansion.
ParsedTargetAttr AArch64TargetInfo::parseTargetAttr(StringRef Features) const {
ParsedTargetAttr Ret;
if (Features == "default")
@@ -1112,23 +1073,26 @@ ParsedTargetAttr AArch64TargetInfo::parseTargetAttr(StringRef Features) const {
bool FoundArch = false;
auto SplitAndAddFeatures = [](StringRef FeatString,
- std::vector<std::string> &Features) {
+ std::vector<std::string> &Features,
+ llvm::AArch64::ExtensionSet &FeatureBits) {
SmallVector<StringRef, 8> SplitFeatures;
FeatString.split(SplitFeatures, StringRef("+"), -1, false);
for (StringRef Feature : SplitFeatures) {
- StringRef FeatureName = llvm::AArch64::getArchExtFeature(Feature);
- if (!FeatureName.empty())
- Features.push_back(FeatureName.str());
+ if (FeatureBits.parseModifier(Feature, /* AllowNoDashForm = */ true))
+ continue;
+ // Pass through features that are not extensions, e.g. +v8.1a,
+ // +outline-atomics, -fmv, etc.
+ if (Feature.starts_with("no"))
+ Features.push_back("-" + Feature.drop_front(2).str());
else
- // Pushing the original feature string to give a sema error later on
- // when they get checked.
- if (Feature.starts_with("no"))
- Features.push_back("-" + Feature.drop_front(2).str());
- else
- Features.push_back("+" + Feature.str());
+ Features.push_back("+" + Feature.str());
}
};
+ llvm::AArch64::ExtensionSet FeatureBits;
+ // Reconstruct the bitset from the command line option features.
+ FeatureBits.reconstructFromParsedFeatures(getTargetOpts().FeaturesAsWritten);
+
for (auto &Feature : AttrFeatures) {
Feature = Feature.trim();
if (Feature.starts_with("fpmath="))
@@ -1151,9 +1115,9 @@ ParsedTargetAttr AArch64TargetInfo::parseTargetAttr(StringRef Features) const {
// Ret.Features.
if (!AI)
continue;
- Ret.Features.push_back(AI->ArchFeature.str());
+ FeatureBits.addArchDefaults(*AI);
// Add any extra features, after the +
- SplitAndAddFeatures(Split.second, Ret.Features);
+ SplitAndAddFeatures(Split.second, Ret.Features, FeatureBits);
} else if (Feature.starts_with("cpu=")) {
if (!Ret.CPU.empty())
Ret.Duplicate = "cpu=";
@@ -1163,7 +1127,10 @@ ParsedTargetAttr AArch64TargetInfo::parseTargetAttr(StringRef Features) const {
std::pair<StringRef, StringRef> Split =
Feature.split("=").second.trim().split("+");
Ret.CPU = Split.first;
- SplitAndAddFeatures(Split.second, Ret.Features);
+ if (auto CpuInfo = llvm::AArch64::parseCpu(Ret.CPU)) {
+ FeatureBits.addCPUDefaults(*CpuInfo);
+ SplitAndAddFeatures(Split.second, Ret.Features, FeatureBits);
+ }
}
} else if (Feature.starts_with("tune=")) {
if (!Ret.Tune.empty())
@@ -1171,25 +1138,19 @@ ParsedTargetAttr AArch64TargetInfo::parseTargetAttr(StringRef Features) const {
else
Ret.Tune = Feature.split("=").second.trim();
} else if (Feature.starts_with("+")) {
- SplitAndAddFeatures(Feature, Ret.Features);
- } else if (Feature.starts_with("no-")) {
- StringRef FeatureName =
- llvm::AArch64::getArchExtFeature(Feature.split("-").second);
- if (!FeatureName.empty())
- Ret.Features.push_back("-" + FeatureName.drop_front(1).str());
- else
- Ret.Features.push_back("-" + Feature.split("-").second.str());
+ SplitAndAddFeatures(Feature, Ret.Features, FeatureBits);
} else {
- // Try parsing the string to the internal target feature name. If it is
- // invalid, add the original string (which could already be an internal
- // name). These should be checked later by isValidFeatureName.
- StringRef FeatureName = llvm::AArch64::getArchExtFeature(Feature);
- if (!FeatureName.empty())
- Ret.Features.push_back(FeatureName.str());
+ if (FeatureBits.parseModifier(Feature, /* AllowNoDashForm = */ true))
+ continue;
+ // Pass through features that are not extensions, e.g. +v8.1a,
+ // +outline-atomics, -fmv, etc.
+ if (Feature.starts_with("no-"))
+ Ret.Features.push_back("-" + Feature.drop_front(3).str());
else
Ret.Features.push_back("+" + Feature.str());
}
}
+ FeatureBits.toLLVMFeatureList(Ret.Features);
return Ret;
}
diff --git a/clang/lib/Basic/Targets/AArch64.h b/clang/lib/Basic/Targets/AArch64.h
index 12fb50286f751..696553ef8038a 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -107,10 +107,6 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo {
unsigned multiVersionSortPriority(StringRef Name) const override;
unsigned multiVersionFeatureCost() const override;
- bool
- initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
- StringRef CPU,
- const std::vector<std::string> &FeaturesVec) const override;
bool useFP16ConversionIntrinsics() const override {
return false;
}
diff --git a/clang/test/CodeGen/aarch64-cpu-supports-target.c b/clang/test/CodeGen/aarch64-cpu-supports-target.c
index e023944b24e53..28187bcf74533 100644
--- a/clang/test/CodeGen/aarch64-cpu-supports-target.c
+++ b/clang/test/CodeGen/aarch64-cpu-supports-target.c
@@ -48,5 +48,5 @@ int test_versions() {
return code();
}
// CHECK: attributes #0 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
-// CHECK: attributes #1 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
-// CHECK: attributes #2 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve" }
+// CHECK: attributes #1 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon" }
+// CHECK: attributes #2 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+sve" }
diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/aarch64-sme-attrs.cpp b/clang/test/CodeGen/aarch64-sme-intrinsics/aarch64-sme-attrs.cpp
index af8933d93d6cb..9885ac45e6a0e 100644
--- a/clang/test/CodeGen/aarch64-sme-intrinsics/aarch64-sme-attrs.cpp
+++ b/clang/test/CodeGen/aarch64-sme-intrinsics/aarch64-sme-attrs.cpp
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme \
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +bf16 \
// RUN: -disable-O0-optnone -Werror -emit-llvm -o - %s \
// RUN: | opt -S -passes=mem2reg \
// RUN: | opt -S -passes=inline \
diff --git a/clang/test/CodeGen/aarch64-targetattr.c b/clang/test/CodeGen/aarch64-targetattr.c
index 3e7a209245607..644e6a692c3be 100644
--- a/clang/test/CodeGen/aarch64-targetattr.c
+++ b/clang/test/CodeGen/aarch64-targetattr.c
@@ -58,58 +58,50 @@ void v1msve() {}
// CHECK-LABEL: @plussve() #12
__attribute__((target("+sve")))
void plussve() {}
-// CHECK-LABEL: @plussveplussve2() #13
+// CHECK-LABEL: @plussveplussve2() #12
__attribute__((target("+sve+nosve2")))
void plussveplussve2() {}
-// CHECK-LABEL: @plussveminusnosve2() #13
+// CHECK-LABEL: @plussveminusnosve2() #12
__attribute__((target("sve,no-sve2")))
void plussveminusnosve2() {}
-// CHECK-LABEL: @plusfp16() #14
+// CHECK-LABEL: @plusfp16() #13
__attribute__((target("+fp16")))
void plusfp16() {}
-// CHECK-LABEL: @all() #15
+// CHECK-LABEL: @all() #14
__attribute__((target("cpu=neoverse-n1,tune=cortex-a710,arch=armv8.6-a+sve2")))
void all() {}
-// CHECK-LABEL: @allplusbranchprotection() #16
+// CHECK-LABEL: @allplusbranchprotection() #15
__attribute__((target("cpu=neoverse-n1,tune=cortex-a710,arch=armv8.6-a+sve2,branch-protection=standard")))
void allplusbranchprotection() {}
-// These tests check that the user facing and internal llvm name are both accepted.
-// CHECK-LABEL: @plusnoneon() #17
-__attribute__((target("+noneon")))
-void plusnoneon() {}
-// CHECK-LABEL: @plusnosimd() #17
+// CHECK-LABEL: @plusnosimd() #16
__attribute__((target("+nosimd")))
void plusnosimd() {}
-// CHECK-LABEL: @noneon() #17
-__attribute__((target("no-neon")))
-void noneon() {}
-// CHECK-LABEL: @nosimd() #17
+// CHECK-LABEL: @nosimd() #16
__attribute__((target("no-simd")))
void nosimd() {}
// This isn't part of the standard interface, but test that -arch features should not apply anything else.
-// CHECK-LABEL: @minusarch() #18
+// CHECK-LABEL: @minusarch() #17
__attribute__((target("no-v9.3a")))
void minusarch() {}
// CHECK: attributes #0 = { {{.*}} "target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" }
// CHECK: attributes #1 = { {{.*}} "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a" }
// CHECK: attributes #2 = { {{.*}} "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a" }
-// CHECK: attributes #3 = { {{.*}} "target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" }
-// CHECK: attributes #4 = { {{.*}} "target-cpu"="cortex-a710" "target-features"="+bf16,+complxnum,+crc,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm" }
+// CHECK: attributes #3 = { {{.*}} "target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" }
+// CHECK: attributes #4 = { {{.*}} "target-cpu"="cortex-a710" "target-features"="+bf16,+complxnum,+crc,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a" }
// CHECK: attributes #5 = { {{.*}} "tune-cpu"="cortex-a710" }
// CHECK: attributes #6 = { {{.*}} "target-cpu"="generic" }
// CHECK: attributes #7 = { {{.*}} "tune-cpu"="generic" }
-// CHECK: attributes #8 = { {{.*}} "target-cpu"="neoverse-n1" "target-features"="+aes,+crc,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs" "tune-cpu"="cortex-a710" }
-// CHECK: attributes #9 = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+sve" "tune-cpu"="cortex-a710" }
-// CHECK: attributes #10 = { {{.*}} "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2" }
-// CHECK: attributes #11 = { {{.*}} "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,-sve" }
-// CHECK: attributes #12 = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+sve" }
-// CHECK: attributes #13 = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+sve,-sve2" }
-// CHECK: attributes #14 = { {{.*}} "target-features"="+fullfp16" }
-// CHECK: attributes #15 = { {{.*}} "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
-// CHECK: attributes #16 = { {{.*}} "branch-target-enforcement"="true" "guarded-control-stack"="true" {{.*}} "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
-// CHECK: attributes #17 = { {{.*}} "target-features"="-neon" }
-// CHECK: attributes #18 = { {{.*}} "target-features"="-v9.3a" }
+// CHECK: attributes #8 = { {{.*}} "target-cpu"="neoverse-n1" "target-features"="+aes,+crc,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+v8.1a,+v8.2a,+v8a" "tune-cpu"="cortex-a710" }
+// CHECK: attributes #9 = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+sve" "tune-cpu"="cortex-a710" }
+// CHECK: attributes #10 = { {{.*}} "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a" }
+// CHECK: attributes #11 = { {{.*}} "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,-sve" }
+// CHECK: attributes #12 = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+sve" }
+// CHECK: attributes #13 = { {{.*}} "target-features"="+fp-armv8,+fullfp16" }
+// CHECK: attributes #14 = { {{.*}} "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
+// CHECK: attributes #15 = { {{.*}} "branch-target-enforcement"="true" "guarded-control-stack"="true" {{.*}} "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
+// CHECK-NOT: attributes #16 = {{.*}} "target-features"
+// CHECK: attributes #17 = { {{.*}} "target-features"="-v9.3a" }
diff --git a/clang/test/CodeGen/attr-target-version.c b/clang/test/CodeGen/attr-target-version.c
index 3597711333d34..75f8734e5aaf3 100644
--- a/clang/test/CodeGen/attr-target-version.c
+++ b/clang/test/CodeGen/attr-target-version.c
@@ -1129,42 +1129,42 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
// CHECK-NOFMV-NEXT: ret i32 0
//
//.
-// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+flagm,+fp16fml,+fullfp16,+neon,+rand,-fp-armv8,-v9.5a" }
+// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+flagm,+fp-armv8,+fp16fml,+fullfp16,+neon,+rand,-v9.5a" }
// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+altnzcv,+bf16,+flagm,+sme,+sme-i16i64,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+lse,+neon,+sha2,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+dotprod,+ls64,+neon,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp16fml,+fullfp16,+neon,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,-fp-armv8,-v9.5a" }
+// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+lse,+neon,+sha2,-v9.5a" }
+// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+dotprod,+fp-armv8,+ls64,+neon,-v9.5a" }
+// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fp16fml,+fullfp16,+neon,-v9.5a" }
+// CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,-v9.5a" }
// CHECK: attributes #[[ATTR6]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,-fp-armv8,-v9.5a" }
// CHECK: attributes #[[ATTR7]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,-fp-armv8,-v9.5a" }
// CHECK: attributes #[[ATTR8]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sme,+sme2,-fp-armv8,-v9.5a" }
// CHECK: attributes #[[ATTR9:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fp-armv8,-v9.5a" }
// CHECK: attributes #[[ATTR10]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ccpp,-fp-armv8,-v9.5a" }
// CHECK: attributes #[[ATTR11]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR12]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon,-fp-armv8,-v9.5a" }
+// CHECK: attributes #[[ATTR12]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,-v9.5a" }
// CHECK: attributes #[[ATTR13]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sb,-fp-armv8,-v9.5a" }
// CHECK: attributes #[[ATTR14]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+mops,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+dotprod,+neon,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR16]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon,+sve,-fp-armv8,-v9.5a" }
+// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+dotprod,+fp-armv8,+neon,-v9.5a" }
+// CHECK: attributes #[[ATTR16]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,-v9.5a" }
// CHECK: attributes #[[ATTR17]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+lse,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR18]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,+rdm,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR19:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+jsconv,+neon,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR20:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,+rdm,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR21]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+jsconv,+neon,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR22]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+aes,+f64mm,+fullfp16,+neon,+sve,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR23]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+complxnum,+fullfp16,+neon,+rdm,+sme,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR24]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f32mm,+fullfp16,+i8mm,+neon,+sha2,+sha3,+sve,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR25]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+dit,+fullfp16,+neon,+sve,-fp-armv8,-v9.5a" }
+// CHECK: attributes #[[ATTR18]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+rdm,-v9.5a" }
+// CHECK: attributes #[[ATTR19:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+jsconv,+neon,-v9.5a" }
+// CHECK: attributes #[[ATTR20:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+rdm,-v9.5a" }
+// CHECK: attributes #[[ATTR21]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+jsconv,+neon,-v9.5a" }
+// CHECK: attributes #[[ATTR22]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+aes,+f64mm,+fp-armv8,+fullfp16,+neon,+sve,-v9.5a" }
+// CHECK: attributes #[[ATTR23]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+complxnum,+fp-armv8,+fullfp16,+neon,+rdm,+sme,-v9.5a" }
+// CHECK: attributes #[[ATTR24]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f32mm,+fp-armv8,+fullfp16,+i8mm,+neon,+sha2,+sha3,+sve,-v9.5a" }
+// CHECK: attributes #[[ATTR25]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+dit,+fp-armv8,+fullfp16,+neon,+sve,-v9.5a" }
// CHECK: attributes #[[ATTR26]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ccpp,+rcpc,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR27]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ccdp,+ccpp,+jsconv,+neon,-fp-armv8,-v9.5a" }
+// CHECK: attributes #[[ATTR27]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ccdp,+ccpp,+fp-armv8,+jsconv,+neon,-v9.5a" }
// CHECK: attributes #[[ATTR28]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fptoint,+rcpc,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR29]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+fullfp16,+neon,+sve,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR30]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon,+sve,+sve2,+sve2-aes,+sve2-sha3,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR31]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon,+sve,+sve2,+sve2-aes,+sve2-bitperm,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR32]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+mte,+neon,+sve,+sve2,+sve2-sm4,-fp-armv8,-v9.5a" }
+// CHECK: attributes #[[ATTR29]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+fp-armv8,+fullfp16,+neon,+sve,-v9.5a" }
+// CHECK: attributes #[[ATTR30]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-aes,+sve2-sha3,-v9.5a" }
+// CHECK: attributes #[[ATTR31]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-aes,+sve2-bitperm,-v9.5a" }
+// CHECK: attributes #[[ATTR32]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+mte,+neon,+sve,+sve2,+sve2-sm4,-v9.5a" }
// CHECK: attributes #[[ATTR33]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+mops,+mte,+rcpc,+rcpc3,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR34]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,+sm4,-fp-armv8,-v9.5a" }
-// CHECK: attributes #[[ATTR35]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+lse,+neon,+rdm,-fp-armv8,-v9.5a" }
+// CHECK: attributes #[[ATTR34]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+sm4,-v9.5a" }
+// CHECK: attributes #[[ATTR35]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+lse,+neon,+rdm,-v9.5a" }
//.
// CHECK-NOFMV: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" }
// CHECK-NOFMV: attributes #[[ATTR1:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" }
diff --git a/clang/test/Sema/aarch64-neon-target.c b/clang/test/Sema/aarch64-neon-target.c
index fa45fff1d183d..642afddd88c15 100644
--- a/clang/test/Sema/aarch64-neon-target.c
+++ b/clang/test/Sema/aarch64-neon-target.c
@@ -69,8 +69,8 @@ void undefined(uint32x2_t v2i32, uint32x4_t v4i32, uint16x8_t v8i16, uint8x16_t
vrnd_f16(v4f16); // expected-error {{always_inline function 'vrnd_f16' requires target feature 'fullfp16'}}
vmaxnm_f16(v4f16, v4f16); // expected-error {{always_inline function 'vmaxnm_f16' requires target feature 'fullfp16'}}
vrndi_f16(v4f16); // expected-error {{always_inline function 'vrndi_f16' requires target feature 'fullfp16'}}
- // fp16fml
- vfmlal_low_f16(v2f32, v4f16, v4f16); // expected-error {{always_inline function 'vfmlal_low_f16' requires target feature 'fp16fml'}}
+ // fp16fml depends on fp-armv8
+ vfmlal_low_f16(v2f32, v4f16, v4f16); // expected-error {{always_inline function 'vfmlal_low_f16' requires target feature 'fp-armv8'}}
// i8mm
vmmlaq_s32(v4i32, v8i16, v8i16); // expected-error {{always_inline function 'vmmlaq_s32' requires target feature 'i8mm'}}
vusdot_laneq_s32(v2i32, v8i8, v8i16, 0); // expected-error {{always_inline function 'vusdot_s32' requires target feature 'i8mm'}}
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index df8e685eb6667..9da4bf4471c9b 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -132,48 +132,6 @@ struct ExtensionInfo {
#define EMIT_EXTENSIONS
#include "llvm/TargetParser/AArch64TargetParserDef.inc"
-struct ExtensionSet {
- // Set of extensions which are currently enabled.
- ExtensionBitset Enabled;
- // Set of extensions which have been enabled or disabled at any point. Used
- // to avoid cluttering the cc1 command-line with lots of unneeded features.
- ExtensionBitset Touched;
- // Base architecture version, which we need to know because some feature
- // dependencies change depending on this.
- const ArchInfo *BaseArch;
-
- ExtensionSet() : Enabled(), Touched(), BaseArch(nullptr) {}
-
- // Enable the given architecture extension, and any other extensions it
- // depends on. Does not change the base architecture, or follow dependencies
- // between features which are only related by required arcitecture versions.
- void enable(ArchExtKind E);
-
- // Disable the given architecture extension, and any other extensions which
- // depend on it. Does not change the base architecture, or follow
- // dependencies between features which are only related by required
- // arcitecture versions.
- void disable(ArchExtKind E);
-
- // Add default extensions for the given CPU. Records the base architecture,
- // to later resolve dependencies which depend on it.
- void addCPUDefaults(const CpuInfo &CPU);
-
- // Add default extensions for the given architecture version. Records the
- // base architecture, to later resolve dependencies which depend on it.
- void addArchDefaults(const ArchInfo &Arch);
-
- // Add or remove a feature based on a modifier string. The string must be of
- // the form "<name>" to enable a feature or "no<name>" to disable it. This
- // will also enable or disable any features as required by the dependencies
- // between them.
- bool parseModifier(StringRef Modifier);
-
- // Convert the set of enabled extension to an LLVM feature list, appending
- // them to Features.
- void toLLVMFeatureList(std::vector<StringRef> &Features) const;
-};
-
// Represents a dependency between two architecture extensions. Later is the
// feature which was added to the architecture after Earlier, and expands the
// functionality provided by it. If Later is enabled, then Earlier will also be
@@ -596,6 +554,65 @@ inline constexpr CpuInfo CpuInfos[] = {
AArch64::AEK_PROFILE}))},
};
+struct ExtensionSet {
+ // Set of extensions which are currently enabled.
+ ExtensionBitset Enabled;
+ // Set of extensions which have been enabled or disabled at any point. Used
+ // to avoid cluttering the cc1 command-line with lots of unneeded features.
+ ExtensionBitset Touched;
+ // Base architecture version, which we need to know because some feature
+ // dependencies change depending on this.
+ const ArchInfo *BaseArch;
+
+ ExtensionSet() : Enabled(), Touched(), BaseArch(nullptr) {}
+
+ // Enable the given architecture extension, and any other extensions it
+ // depends on. Does not change the base architecture, or follow dependencies
+ // between features which are only related by required arcitecture versions.
+ void enable(ArchExtKind E);
+
+ // Disable the given architecture extension, and any other extensions which
+ // depend on it. Does not change the base architecture, or follow
+ // dependencies between features which are only related by required
+ // arcitecture versions.
+ void disable(ArchExtKind E);
+
+ // Add default extensions for the given CPU. Records the base architecture,
+ // to later resolve dependencies which depend on it.
+ void addCPUDefaults(const CpuInfo &CPU);
+
+ // Add default extensions for the given architecture version. Records the
+ // base architecture, to later resolve dependencies which depend on it.
+ void addArchDefaults(const ArchInfo &Arch);
+
+ // Add or remove a feature based on a modifier string. The string must be of
+ // the form "<name>" to enable a feature or "no<name>" to disable it. This
+ // will also enable or disable any features as required by the dependencies
+ // between them.
+ bool parseModifier(StringRef Modifier, const bool AllowNoDashForm = false);
+
+ // Constructs a new ExtensionSet by toggling the corresponding bits for every
+ // feature in the \p Features list without expanding their dependencies. Used
+ // for reconstructing an ExtensionSet from the output of toLLVMFeatures().
+ void reconstructFromParsedFeatures(const std::vector<std::string> &Features);
+
+ // Convert the set of enabled extension to an LLVM feature list, appending
+ // them to Features.
+ template <typename T> void toLLVMFeatureList(std::vector<T> &Features) const {
+ if (BaseArch && !BaseArch->ArchFeature.empty())
+ Features.emplace_back(T(BaseArch->ArchFeature));
+
+ for (const auto &E : Extensions) {
+ if (E.Feature.empty() || !Touched.test(E.ID))
+ continue;
+ if (Enabled.test(E.ID))
+ Features.emplace_back(T(E.Feature));
+ else
+ Features.emplace_back(T(E.NegFeature));
+ }
+ }
+};
+
// Name alias.
struct Alias {
StringRef AltName;
@@ -619,7 +636,13 @@ const ArchInfo *getArchForCpu(StringRef CPU);
// Parser
const ArchInfo *parseArch(StringRef Arch);
+
+// Return the extension which has the given -target-feature name.
+std::optional<ExtensionInfo> targetFeatureToExtension(StringRef TargetFeature);
+
+// Parse a name as defined by the Extension class in tablegen.
std::optional<ExtensionInfo> parseArchExtension(StringRef Extension);
+
// Given the name of a CPU or alias, return the correponding CpuInfo.
std::optional<CpuInfo> parseCpu(StringRef Name);
// Used by target parser tests
diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp b/llvm/lib/TargetParser/AArch64TargetParser.cpp
index ca356ec82bf1f..d1cc306790522 100644
--- a/llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -122,6 +122,14 @@ AArch64::parseArchExtension(StringRef ArchExt) {
return {};
}
+std::optional<AArch64::ExtensionInfo>
+AArch64::targetFeatureToExtension(StringRef TargetFeature) {
+ for (const auto &E : Extensions)
+ if (TargetFeature == E.Feature)
+ return E;
+ return {};
+}
+
std::optional<AArch64::CpuInfo> AArch64::parseCpu(StringRef Name) {
// Resolve aliases first.
Name = resolveCPUAlias(Name);
@@ -213,21 +221,6 @@ void AArch64::ExtensionSet::disable(ArchExtKind E) {
disable(Dep.Later);
}
-void AArch64::ExtensionSet::toLLVMFeatureList(
- std::vector<StringRef> &Features) const {
- if (BaseArch && !BaseArch->ArchFeature.empty())
- Features.push_back(BaseArch->ArchFeature);
-
- for (const auto &E : Extensions) {
- if (E.Feature.empty() || !Touched.test(E.ID))
- continue;
- if (Enabled.test(E.ID))
- Features.push_back(E.Feature);
- else
- Features.push_back(E.NegFeature);
- }
-}
-
void AArch64::ExtensionSet::addCPUDefaults(const CpuInfo &CPU) {
LLVM_DEBUG(llvm::dbgs() << "addCPUDefaults(" << CPU.Name << ")\n");
BaseArch = &CPU.Arch;
@@ -247,11 +240,18 @@ void AArch64::ExtensionSet::addArchDefaults(const ArchInfo &Arch) {
enable(E.ID);
}
-bool AArch64::ExtensionSet::parseModifier(StringRef Modifier) {
+bool AArch64::ExtensionSet::parseModifier(StringRef Modifier,
+ const bool AllowNoDashForm) {
LLVM_DEBUG(llvm::dbgs() << "parseModifier(" << Modifier << ")\n");
- bool IsNegated = Modifier.starts_with("no");
- StringRef ArchExt = IsNegated ? Modifier.drop_front(2) : Modifier;
+ size_t NChars = 0;
+ // The "no-feat" form is allowed in the target attribute but nowhere else.
+ if (AllowNoDashForm && Modifier.starts_with("no-"))
+ NChars = 3;
+ else if (Modifier.starts_with("no"))
+ NChars = 2;
+ bool IsNegated = NChars != 0;
+ StringRef ArchExt = Modifier.drop_front(NChars);
if (auto AE = parseArchExtension(ArchExt)) {
if (AE->Feature.empty() || AE->NegFeature.empty())
@@ -265,6 +265,21 @@ bool AArch64::ExtensionSet::parseModifier(StringRef Modifier) {
return false;
}
+void AArch64::ExtensionSet::reconstructFromParsedFeatures(
+ const std::vector<std::string> &Features) {
+ assert(Touched.none() && "Bitset already initialized");
+ for (auto &F : Features) {
+ bool IsNegated = F[0] == '-';
+ if (auto AE = targetFeatureToExtension(F)) {
+ Touched.set(AE->ID);
+ if (IsNegated)
+ Enabled.reset(AE->ID);
+ else
+ Enabled.set(AE->ID);
+ }
+ }
+}
+
const AArch64::ExtensionInfo &
AArch64::getExtensionByID(AArch64::ArchExtKind ExtID) {
return lookupExtensionByID(ExtID);
>From 442e4eef2001fbf65a95236d8afb547e82bf92d0 Mon Sep 17 00:00:00 2001
From: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: Fri, 14 Jun 2024 09:10:23 +0100
Subject: [PATCH 5/7] Changes from last revision:
* We should be inserting the Driver features in front of the features
of a parsed target attribute.
* Added a sema test.
---
clang/lib/AST/ASTContext.cpp | 10 ++++------
clang/test/Sema/aarch64-neon-target.c | 6 ++++++
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index aa22825602a40..7fb5966c0bf7c 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -13725,12 +13725,10 @@ void ASTContext::getFunctionFeatureMap(llvm::StringMap<bool> &FeatureMap,
// Make a copy of the features as passed on the command line into the
// beginning of the additional features from the function to override.
- // AArch64 handles command line option features in parseTargetAttr().
- if (!Target->getTriple().isAArch64())
- ParsedAttr.Features.insert(
- ParsedAttr.Features.begin(),
- Target->getTargetOpts().FeaturesAsWritten.begin(),
- Target->getTargetOpts().FeaturesAsWritten.end());
+ ParsedAttr.Features.insert(
+ ParsedAttr.Features.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.end());
if (ParsedAttr.CPU != "" && Target->isValidCPUName(ParsedAttr.CPU))
TargetCPU = ParsedAttr.CPU;
diff --git a/clang/test/Sema/aarch64-neon-target.c b/clang/test/Sema/aarch64-neon-target.c
index 642afddd88c15..fd84b7f2eb00a 100644
--- a/clang/test/Sema/aarch64-neon-target.c
+++ b/clang/test/Sema/aarch64-neon-target.c
@@ -1,4 +1,5 @@
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -verify -emit-llvm -o - %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +outline-atomics -verify -emit-llvm -o - %s
// REQUIRES: aarch64-registered-target
// Test that functions with the correct target attributes can use the correct NEON intrinsics.
@@ -41,6 +42,11 @@ void bf16(uint32x2_t v2i32, uint32x4_t v4i32, uint16x8_t v8i16, uint8x16_t v16i8
vcvt_bf16_f32(v4f32);
}
+__attribute__((target("arch=armv8-a")))
+uint64x2_t test_v8(uint64x2_t a, uint64x2_t b) {
+ return veorq_u64(a, b);
+}
+
__attribute__((target("arch=armv8.1-a")))
void test_v81(int32x2_t d, int32x4_t v, int s) {
vqrdmlahq_s32(v, v, v);
>From cf4dcdb9972d6bc0dd1ab879f211c4aaf174b8b5 Mon Sep 17 00:00:00 2001
From: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: Fri, 14 Jun 2024 12:27:33 +0100
Subject: [PATCH 6/7] Changes from last revision:
* Revert inserting the Driver features in front of the features
of a parsed target attribute.
* Instead make reconstructFromParsedFeatures() add unrecognized
features to the features of a parsed target attribute.
* Do not allow 'no-' form when parsing '+' separated features.
* Updated misleading comments and added FIXMEs.
---
clang/lib/AST/ASTContext.cpp | 10 ++++---
clang/lib/Basic/Targets/AArch64.cpp | 26 ++++++++++++-------
.../llvm/TargetParser/AArch64TargetParser.h | 4 ++-
llvm/lib/TargetParser/AArch64TargetParser.cpp | 5 +++-
4 files changed, 30 insertions(+), 15 deletions(-)
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 7fb5966c0bf7c..aa22825602a40 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -13725,10 +13725,12 @@ void ASTContext::getFunctionFeatureMap(llvm::StringMap<bool> &FeatureMap,
// Make a copy of the features as passed on the command line into the
// beginning of the additional features from the function to override.
- ParsedAttr.Features.insert(
- ParsedAttr.Features.begin(),
- Target->getTargetOpts().FeaturesAsWritten.begin(),
- Target->getTargetOpts().FeaturesAsWritten.end());
+ // AArch64 handles command line option features in parseTargetAttr().
+ if (!Target->getTriple().isAArch64())
+ ParsedAttr.Features.insert(
+ ParsedAttr.Features.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.end());
if (ParsedAttr.CPU != "" && Target->isValidCPUName(ParsedAttr.CPU))
TargetCPU = ParsedAttr.CPU;
diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
index 6fba5fff7bcc1..a43937de819cf 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -1061,9 +1061,8 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
//
// A feature may correspond to an Extension (anything with a corresponding
// AEK_), in which case an ExtensionSet is used to parse it and expand its
-// dependencies. Otherwise the feature is passed through (e.g. +v8.1a,
-// +outline-atomics, -fmv, etc). Features coming from the command line are
-// already parsed, therefore their dependencies do not need expansion.
+// dependencies. If the feature does not yield a successful parse then it
+// is be passed through.
ParsedTargetAttr AArch64TargetInfo::parseTargetAttr(StringRef Features) const {
ParsedTargetAttr Ret;
if (Features == "default")
@@ -1078,10 +1077,14 @@ ParsedTargetAttr AArch64TargetInfo::parseTargetAttr(StringRef Features) const {
SmallVector<StringRef, 8> SplitFeatures;
FeatString.split(SplitFeatures, StringRef("+"), -1, false);
for (StringRef Feature : SplitFeatures) {
- if (FeatureBits.parseModifier(Feature, /* AllowNoDashForm = */ true))
+ if (FeatureBits.parseModifier(Feature))
continue;
- // Pass through features that are not extensions, e.g. +v8.1a,
- // +outline-atomics, -fmv, etc.
+ // Pass through anything that failed to parse so that we can emit
+ // diagnostics, as well as valid internal feature names.
+ //
+ // FIXME: We should consider rejecting internal feature names like
+ // neon, v8a, etc.
+ // FIXME: We should consider emitting diagnostics here.
if (Feature.starts_with("no"))
Features.push_back("-" + Feature.drop_front(2).str());
else
@@ -1091,7 +1094,8 @@ ParsedTargetAttr AArch64TargetInfo::parseTargetAttr(StringRef Features) const {
llvm::AArch64::ExtensionSet FeatureBits;
// Reconstruct the bitset from the command line option features.
- FeatureBits.reconstructFromParsedFeatures(getTargetOpts().FeaturesAsWritten);
+ FeatureBits.reconstructFromParsedFeatures(getTargetOpts().FeaturesAsWritten,
+ Ret.Features);
for (auto &Feature : AttrFeatures) {
Feature = Feature.trim();
@@ -1142,8 +1146,12 @@ ParsedTargetAttr AArch64TargetInfo::parseTargetAttr(StringRef Features) const {
} else {
if (FeatureBits.parseModifier(Feature, /* AllowNoDashForm = */ true))
continue;
- // Pass through features that are not extensions, e.g. +v8.1a,
- // +outline-atomics, -fmv, etc.
+ // Pass through anything that failed to parse so that we can emit
+ // diagnostics, as well as valid internal feature names.
+ //
+ // FIXME: We should consider rejecting internal feature names like
+ // neon, v8a, etc.
+ // FIXME: We should consider emitting diagnostics here.
if (Feature.starts_with("no-"))
Ret.Features.push_back("-" + Feature.drop_front(3).str());
else
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 9da4bf4471c9b..7b5d59f82d9bd 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -594,7 +594,9 @@ struct ExtensionSet {
// Constructs a new ExtensionSet by toggling the corresponding bits for every
// feature in the \p Features list without expanding their dependencies. Used
// for reconstructing an ExtensionSet from the output of toLLVMFeatures().
- void reconstructFromParsedFeatures(const std::vector<std::string> &Features);
+ // Features that are not recognized are pushed back to \p NonExtensions.
+ void reconstructFromParsedFeatures(const std::vector<std::string> &Features,
+ std::vector<std::string> &NonExtensions);
// Convert the set of enabled extension to an LLVM feature list, appending
// them to Features.
diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp b/llvm/lib/TargetParser/AArch64TargetParser.cpp
index d1cc306790522..0f6a97144e04d 100644
--- a/llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -266,7 +266,8 @@ bool AArch64::ExtensionSet::parseModifier(StringRef Modifier,
}
void AArch64::ExtensionSet::reconstructFromParsedFeatures(
- const std::vector<std::string> &Features) {
+ const std::vector<std::string> &Features,
+ std::vector<std::string> &NonExtensions) {
assert(Touched.none() && "Bitset already initialized");
for (auto &F : Features) {
bool IsNegated = F[0] == '-';
@@ -276,7 +277,9 @@ void AArch64::ExtensionSet::reconstructFromParsedFeatures(
Enabled.reset(AE->ID);
else
Enabled.set(AE->ID);
+ continue;
}
+ NonExtensions.push_back(F);
}
}
>From a7d83638992762fbde60623b2bbe0fa9943ec992 Mon Sep 17 00:00:00 2001
From: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: Fri, 14 Jun 2024 12:45:13 +0100
Subject: [PATCH 7/7] Fix typo
---
clang/lib/Basic/Targets/AArch64.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
index a43937de819cf..418f124c4df56 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -1062,7 +1062,7 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
// A feature may correspond to an Extension (anything with a corresponding
// AEK_), in which case an ExtensionSet is used to parse it and expand its
// dependencies. If the feature does not yield a successful parse then it
-// is be passed through.
+// is passed through.
ParsedTargetAttr AArch64TargetInfo::parseTargetAttr(StringRef Features) const {
ParsedTargetAttr Ret;
if (Features == "default")
More information about the llvm-commits
mailing list