[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
Lucas Duarte Prates via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 18 08:12:33 PDT 2024
================
@@ -140,89 +152,480 @@ def FeatureAES : Extension<
// compatibility, and now imply features SHA2 and AES, which was the
// "traditional" meaning of Crypto.
let FMVDependencies = "+aes,+sha2" in
-def FeatureCrypto : Extension<"crypto", "Crypto",
+def FeatureCrypto : ExtensionWithMArch<"crypto", "Crypto", "FEAT_Crypto",
"Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
-def FeatureCRC : Extension<"crc", "CRC",
- "Enable ARMv8 CRC-32 checksum instructions (FEAT_CRC32)", [],
+def FeatureCRC : ExtensionWithMArch<"crc", "CRC", "FEAT_CRC32",
+ "Enable ARMv8 CRC-32 checksum instructions", [],
"FEAT_CRC", "+crc", 110>;
-def FeatureRAS : Extension<"ras", "RAS",
- "Enable ARMv8 Reliability, Availability and Serviceability Extensions (FEAT_RAS, FEAT_RASv1p1)">;
-
-def FeatureRASv2 : Extension<"rasv2", "RASv2",
- "Enable ARMv8.9-A Reliability, Availability and Serviceability Extensions (FEAT_RASv2)",
- [FeatureRAS]>;
-
-def FeatureLSE : Extension<"lse", "LSE",
- "Enable ARMv8.1 Large System Extension (LSE) atomic instructions (FEAT_LSE)", [],
- "FEAT_LSE", "+lse", 80>;
+// This SubtargetFeature is special. It controls only whether codegen will turn
+// `llvm.readcyclecounter()` into an access to a PMUv3 System Register. The
+// `FEAT_PMUv3*` system registers are always available for assembly/disassembly.
+let MArchName = "pmuv3" in
+def FeaturePerfMon : ExtensionWithMArch<"perfmon", "PerfMon", "FEAT_PMUv3",
+ "Enable Code Generation for ARMv8 PMUv3 Performance Monitors extension">;
-def FeatureLSE2 : SubtargetFeature<"lse2", "HasLSE2", "true",
- "Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules (FEAT_LSE2)">;
+def FeatureSpecRestrict : Extension<"specrestrict", "SpecRestrict", "FEAT_CSV2_2",
+ "Enable architectural speculation restriction">;
-def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true",
- "Enable out of line atomics to support LSE instructions">;
+//===----------------------------------------------------------------------===//
+// Armv8.1 Architecture Extensions
+//===----------------------------------------------------------------------===//
-def FeatureFMV : SubtargetFeature<"fmv", "HasFMV", "true",
- "Enable Function Multi Versioning support.">;
+def FeatureLSE : ExtensionWithMArch<"lse", "LSE", "FEAT_LSE",
+ "Enable ARMv8.1 Large System Extension (LSE) atomic instructions", [],
+ "FEAT_LSE", "+lse", 80>;
let MArchAlias = "rdma" in
-def FeatureRDM : Extension<"rdm", "RDM",
- "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions (FEAT_RDM)",
+def FeatureRDM : ExtensionWithMArch<"rdm", "RDM", "FEAT_RDM",
+ "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions",
[FeatureNEON],
"FEAT_RDM", "+rdm,+fp-armv8,+neon", 108>;
-def FeaturePAN : SubtargetFeature<
- "pan", "HasPAN", "true",
- "Enables ARM v8.1 Privileged Access-Never extension (FEAT_PAN)">;
+def FeaturePAN : Extension<"pan", "PAN", "FEAT_PAN",
+ "Enables ARM v8.1 Privileged Access-Never extension">;
-def FeatureLOR : SubtargetFeature<
- "lor", "HasLOR", "true",
- "Enables ARM v8.1 Limited Ordering Regions extension (FEAT_LOR)">;
+def FeatureLOR : Extension<"lor", "LOR", "FEAT_LOR",
+ "Enables ARM v8.1 Limited Ordering Regions extension">;
def FeatureCONTEXTIDREL2 : SubtargetFeature<"CONTEXTIDREL2", "HasCONTEXTIDREL2",
"true", "Enable RW operand CONTEXTIDR_EL2" >;
-def FeatureVH : SubtargetFeature<"vh", "HasVH", "true",
- "Enables ARM v8.1 Virtual Host extension (FEAT_VHE)", [FeatureCONTEXTIDREL2] >;
+def FeatureVH : Extension<"vh", "VH", "FEAT_VHE",
+ "Enables ARM v8.1 Virtual Host extension", [FeatureCONTEXTIDREL2] >;
-// This SubtargetFeature is special. It controls only whether codegen will turn
-// `llvm.readcyclecounter()` into an access to a PMUv3 System Register. The
-// `FEAT_PMUv3*` system registers are always available for assembly/disassembly.
-let MArchName = "pmuv3" in
-def FeaturePerfMon : Extension<"perfmon", "PerfMon",
- "Enable Code Generation for ARMv8 PMUv3 Performance Monitors extension (FEAT_PMUv3)">;
+//===----------------------------------------------------------------------===//
+// Armv8.2 Architecture Extensions
+//===----------------------------------------------------------------------===//
+
+def FeatureSM4 : ExtensionWithMArch<"sm4", "SM4", "FEAT_SM4, FEAT_SM3",
+ "Enable SM3 and SM4 support", [FeatureNEON],
+ "FEAT_SM4", "+sm4,+fp-armv8,+neon", 106>;
+
+def FeatureSHA3 : ExtensionWithMArch<"sha3", "SHA3", "FEAT_SHA3, FEAT_SHA512",
+ "Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2],
+ "FEAT_SHA3", "+sha3,+sha2,+fp-armv8,+neon", 140>;
+
+def FeatureRAS : ExtensionWithMArch<"ras", "RAS", "FEAT_RAS, FEAT_RASv1p1",
+ "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
let ArchExtKindSpelling = "AEK_FP16", MArchName = "fp16" in
-def FeatureFullFP16 : Extension<"fullfp16", "FullFP16",
- "Full FP16 (FEAT_FP16)", [FeatureFPARMv8],
+def FeatureFullFP16 : ExtensionWithMArch<"fullfp16", "FullFP16", "FEAT_FP16",
+ "Full FP16", [FeatureFPARMv8],
"FEAT_FP16", "+fullfp16,+fp-armv8,+neon", 170>;
-def FeatureFP16FML : Extension<"fp16fml", "FP16FML",
- "Enable FP16 FML instructions (FEAT_FHM)", [FeatureFullFP16],
- "FEAT_FP16FML", "+fp16fml,+fullfp16,+fp-armv8,+neon", 175>;
-
let ArchExtKindSpelling = "AEK_PROFILE", MArchName = "profile" in
-def FeatureSPE : Extension<"spe", "SPE",
- "Enable Statistical Profiling extension (FEAT_SPE)">;
+def FeatureSPE : ExtensionWithMArch<"spe", "SPE", "FEAT_SPE",
+ "Enable Statistical Profiling extension">;
-def FeaturePAN_RWV : SubtargetFeature<
- "pan-rwv", "HasPAN_RWV", "true",
- "Enable v8.2 PAN s1e1R and s1e1W Variants (FEAT_PAN2)",
- [FeaturePAN]>;
+def FeaturePAN_RWV : Extension<"pan-rwv", "PAN_RWV", "FEAT_PAN2",
+ "Enable v8.2 PAN s1e1R and s1e1W Variants", [FeaturePAN]>;
-// UAO PState
-def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true",
- "Enable v8.2 UAO PState (FEAT_UAO)">;
+def FeaturePsUAO : Extension<"uaops", "PsUAO", "FEAT_UAO",
+ "Enable v8.2 UAO PState">;
-def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP",
- "true", "Enable v8.2 data Cache Clean to Point of Persistence (FEAT_DPB)" >;
+def FeatureCCPP : Extension<"ccpp", "CCPP", "FEAT_DPB",
+ "Enable v8.2 data Cache Clean to Point of Persistence" >;
-def FeatureSVE : Extension<"sve", "SVE",
- "Enable Scalable Vector Extension (SVE) instructions (FEAT_SVE)", [FeatureFullFP16],
+def FeatureSVE : ExtensionWithMArch<"sve", "SVE", "FEAT_SVE",
+ "Enable Scalable Vector Extension (SVE) instructions", [FeatureFullFP16],
"FEAT_SVE", "+sve,+fullfp16,+fp-armv8,+neon", 310>;
+let ArchExtKindSpelling = "AEK_I8MM" in
+def FeatureMatMulInt8 : ExtensionWithMArch<"i8mm", "MatMulInt8", "FEAT_I8MM",
+ "Enable Matrix Multiply Int8 Extension", [],
+ "FEAT_I8MM", "+i8mm", 270>;
+
+let ArchExtKindSpelling = "AEK_F32MM" in
+def FeatureMatMulFP32 : ExtensionWithMArch<"f32mm", "MatMulFP32", "FEAT_F32MM",
+ "Enable Matrix Multiply FP32 Extension", [FeatureSVE],
+ "FEAT_SVE_F32MM", "+sve,+f32mm,+fullfp16,+fp-armv8,+neon", 350>;
+
+let ArchExtKindSpelling = "AEK_F64MM" in
+def FeatureMatMulFP64 : ExtensionWithMArch<"f64mm", "MatMulFP64", "FEAT_F64MM",
+ "Enable Matrix Multiply FP64 Extension", [FeatureSVE],
+ "FEAT_SVE_F64MM", "+sve,+f64mm,+fullfp16,+fp-armv8,+neon", 360>;
+
+//===----------------------------------------------------------------------===//
+// Armv8.3 Architecture Extensions
+//===----------------------------------------------------------------------===//
+
+def FeatureRCPC : ExtensionWithMArch<"rcpc", "RCPC", "FEAT_LRCPC",
+ "Enable support for RCPC extension", [],
+ "FEAT_RCPC", "+rcpc", 230>;
+
+def FeaturePAuth : ExtensionWithMArch<"pauth", "PAuth", "FEAT_PAuth",
+ "Enable v8.3-A Pointer Authentication extension">;
+
+let ArchExtKindSpelling = "AEK_JSCVT", MArchName = "jscvt" in
+def FeatureJS : ExtensionWithMArch<"jsconv", "JS", "FEAT_JSCVT",
+ "Enable v8.3-A JavaScript FP conversion instructions",
+ [FeatureFPARMv8],
+ "FEAT_JSCVT", "+fp-armv8,+neon,+jsconv", 210>;
+
+def FeatureCCIDX : Extension<"ccidx", "CCIDX", "FEAT_CCIDX",
+ "Enable v8.3-A Extend of the CCSIDR number of sets">;
+
+let ArchExtKindSpelling = "AEK_FCMA", MArchName = "fcma" in
+def FeatureComplxNum : ExtensionWithMArch<"complxnum", "ComplxNum", "FEAT_FCMA",
+ "Enable v8.3-A Floating-point complex number support",
+ [FeatureNEON],
+ "FEAT_FCMA", "+fp-armv8,+neon,+complxnum", 220>;
+
+def FeatureNV : Extension<"nv", "NV", "FEAT_NV, FEAT_NV2",
+ "Enable v8.4-A Nested Virtualization Enchancement">;
+
+//===----------------------------------------------------------------------===//
+// Armv8.4 Architecture Extensions
+//===----------------------------------------------------------------------===//
+
+def FeatureLSE2 : Extension<"lse2", "LSE2", "FEAT_LSE2",
+ "Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules">;
+
+def FeatureFP16FML : ExtensionWithMArch<"fp16fml", "FP16FML", "FEAT_FHM",
+ "Enable FP16 FML instructions", [FeatureFullFP16],
+ "FEAT_FP16FML", "+fp16fml,+fullfp16,+fp-armv8,+neon", 175>;
+
+def FeatureDotProd : ExtensionWithMArch<"dotprod", "DotProd", "FEAT_DotProd",
+ "Enable dot product support", [FeatureNEON],
+ "FEAT_DOTPROD", "+dotprod,+fp-armv8,+neon", 104>;
+
+def FeatureMPAM : Extension<"mpam", "MPAM", "FEAT_MPAM",
+ "Enable v8.4-A Memory system Partitioning and Monitoring extension">;
+
+def FeatureDIT : ExtensionWithMArch<"dit", "DIT", "FEAT_DIT",
+ "Enable v8.4-A Data Independent Timing instructions", [],
+ "FEAT_DIT", "+dit", 180>;
+
+def FeatureTRACEV8_4 : Extension<"tracev8.4", "TRACEV8_4", "FEAT_TRF",
+ "Enable v8.4-A Trace extension">;
+
+def FeatureAM : Extension<"am", "AM", "FEAT_AMUv1",
+ "Enable v8.4-A Activity Monitors extension">;
+
+def FeatureSEL2 : Extension<"sel2", "SEL2", "FEAT_SEL2",
+ "Enable v8.4-A Secure Exception Level 2 extension">;
+
+def FeatureTLB_RMI : Extension<"tlb-rmi", "TLB_RMI", "FEAT_TLBIOS, FEAT_TLBIRANGE",
+ "Enable v8.4-A TLB Range and Maintenance Instructions">;
+
+def FeatureFlagM : ExtensionWithMArch<"flagm", "FlagM", "FEAT_FlagM",
+ "Enable v8.4-A Flag Manipulation Instructions", [],
+ "FEAT_FLAGM", "+flagm", 20>;
+
+def FeatureRCPC_IMMO : Extension<"rcpc-immo", "RCPC_IMMO", "FEAT_LRCPC2",
+ "Enable v8.4-A RCPC instructions with Immediate Offsets",
+ [FeatureRCPC]>;
+
+//===----------------------------------------------------------------------===//
+// Armv8.5 Architecture Extensions
+//===----------------------------------------------------------------------===//
+
+def FeatureAltFPCmp : Extension<"altnzcv", "AlternativeNZCV", "FEAT_FlagM2",
+ "Enable alternative NZCV format for floating point comparisons">;
+
+def FeatureFRInt3264 : Extension<"fptoint", "FRInt3264", "FEAT_FRINTTS",
+ "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to "
+ "an integer (in FP format) forcing it to fit into a 32- or 64-bit int" >;
+
+def FeatureSB : ExtensionWithMArch<"sb", "SB", "FEAT_SB",
+ "Enable v8.5 Speculation Barrier", [],
+ "FEAT_SB", "+sb", 470>;
+
+def FeatureSSBS : ExtensionWithMArch<"ssbs", "SSBS", "FEAT_SSBS, FEAT_SSBS2",
+ "Enable Speculative Store Bypass Safe bit", [],
+ "FEAT_SSBS", "", 490>;
+
+def FeaturePredRes : ExtensionWithMArch<"predres", "PredRes", "FEAT_SPECRES",
+ "Enable v8.5a execution and data prediction invalidation instructions", [],
+ "FEAT_PREDRES", "+predres", 480>;
+
+def FeatureCacheDeepPersist : Extension<"ccdp", "CCDP", "FEAT_DPB2",
+ "Enable v8.5 Cache Clean to Point of Deep Persistence" >;
+
+let ArchExtKindSpelling = "AEK_NONE" in
+def FeatureBranchTargetId : ExtensionWithMArch<"bti", "BTI", "FEAT_BTI",
+ "Enable Branch Target Identification", [],
+ "FEAT_BTI", "+bti", 510>;
+
+let ArchExtKindSpelling = "AEK_RAND", MArchName = "rng" in
+def FeatureRandGen : ExtensionWithMArch<"rand", "RandGen", "FEAT_RNG",
+ "Enable Random Number generation instructions", [],
+ "FEAT_RNG", "+rand", 10>;
+
+// NOTE: "memtag" means FEAT_MTE + FEAT_MTE2 for -march or
+// __attribute((target(...))), but only FEAT_MTE for FMV.
+let MArchName = "memtag" in
+def FeatureMTE : ExtensionWithMArch<"mte", "MTE", "FEAT_MTE, FEAT_MTE2",
+ "Enable Memory Tagging Extension", [],
+ "FEAT_MEMTAG", "", 440>;
+
+//===----------------------------------------------------------------------===//
+// Armv8.6 Architecture Extensions
+//===----------------------------------------------------------------------===//
+
+def FeatureBF16 : ExtensionWithMArch<"bf16", "BF16", "FEAT_BF16",
+ "Enable BFloat16 Extension", [],
+ "FEAT_BF16", "+bf16", 280>;
+
+def FeatureAMVS : Extension<"amvs", "AMVS", "FEAT_AMUv1p1",
+ "Enable v8.6-A Activity Monitors Virtualization support",
+ [FeatureAM]>;
+
+def FeatureFineGrainedTraps : Extension<"fgt", "FineGrainedTraps", "FEAT_FGT",
+ "Enable fine grained virtualization traps extension">;
+
+def FeatureEnhancedCounterVirtualization :
+ Extension<"ecv", "EnhancedCounterVirtualization", "FEAT_ECV",
+ "Enable enhanced counter virtualization extension">;
+
+//===----------------------------------------------------------------------===//
+// Armv8.7 Architecture Extensions
+//===----------------------------------------------------------------------===//
+
+def FeatureXS : Extension<"xs", "XS", "FEAT_XS",
+ "Enable Armv8.7-A limited-TLB-maintenance instruction">;
+
+def FeatureWFxT : ExtensionWithMArch<"wfxt", "WFxT", "FEAT_WFxT",
+ "Enable Armv8.7-A WFET and WFIT instruction", [],
+ "FEAT_WFXT", "+wfxt", 550>;
+
+def FeatureHCX : Extension<"hcx", "HCX", "FEAT_HCX",
+ "Enable Armv8.7-A HCRX_EL2 system register">;
+
+def FeatureLS64 : ExtensionWithMArch<"ls64", "LS64", "FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA",
+ "Enable Armv8.7-A LD64B/ST64B Accelerator Extension", [],
+ "FEAT_LS64", "", 520>;
+
+def FeatureSPE_EEF : Extension<"spe-eef", "SPE_EEF", "FEAT_SPEv1p2",
+ "Enable extra register in the Statistical Profiling Extension">;
+
+//===----------------------------------------------------------------------===//
+// Armv8.8 Architecture Extensions
+//===----------------------------------------------------------------------===//
+
+def FeatureHBC : ExtensionWithMArch<"hbc", "HBC", "FEAT_HBC",
+ "Enable Armv8.8-A Hinted Conditional Branches Extension">;
+
+def FeatureMOPS : ExtensionWithMArch<"mops", "MOPS", "FEAT_MOPS",
+ "Enable Armv8.8-A memcpy and memset acceleration instructions", [],
+ "FEAT_MOPS", "+mops", 650>;
+
+def FeatureNMI : Extension<"nmi", "NMI", "FEAT_NMI, FEAT_GICv3_NMI",
+ "Enable Armv8.8-A Non-maskable Interrupts">;
+
+//===----------------------------------------------------------------------===//
+// Armv8.9 Architecture Extensions
+//===----------------------------------------------------------------------===//
+
+def FeatureRASv2 : ExtensionWithMArch<"rasv2", "RASv2", "FEAT_RASv2",
+ "Enable ARMv8.9-A Reliability, Availability and Serviceability Extensions",
+ [FeatureRAS]>;
+
+def FeatureCSSC : ExtensionWithMArch<"cssc", "CSSC", "FEAT_CSSC",
+ "Enable Common Short Sequence Compression (CSSC) instructions">;
+
+def FeatureCLRBHB : Extension<"clrbhb", "CLRBHB", "FEAT_CLRBHB",
+ "Enable Clear BHB instruction">;
+
+def FeaturePRFM_SLC : Extension<"prfm-slc-target", "PRFM_SLC", "FEAT_PRFMSLC",
+ "Enable SLC target for PRFM instruction">;
+
+let MArchName = "predres2" in
+def FeatureSPECRES2 : ExtensionWithMArch<"specres2", "SPECRES2", "FEAT_SPECRES2",
+ "Enable Speculation Restriction Instruction",
+ [FeaturePredRes]>;
+
+def FeatureRCPC3 : ExtensionWithMArch<"rcpc3", "RCPC3", "FEAT_LRCPC3",
+ "Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set",
+ [FeatureRCPC_IMMO],
+ "FEAT_RCPC3", "+rcpc,+rcpc3", 241>;
+
+def FeatureTHE : ExtensionWithMArch<"the", "THE", "FEAT_THE",
+ "Enable Armv8.9-A Translation Hardening Extension">;
+
+//===----------------------------------------------------------------------===//
+// Armv9.0 Architecture Extensions
+//===----------------------------------------------------------------------===//
+
+def FeatureUseScalarIncVL : SubtargetFeature<"use-scalar-inc-vl",
+ "UseScalarIncVL", "true", "Prefer inc/dec over add+cnt">;
----------------
pratlucas wrote:
I'm resolving this here, as it's being covered in https://github.com/llvm/llvm-project/pull/95898#discussion_r1644156524.
https://github.com/llvm/llvm-project/pull/95805
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