[llvm] 3eb4128 - [StackTagging] Generate test checks (NFC)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 18 08:07:06 PDT 2024
Author: Nikita Popov
Date: 2024-06-18T17:06:32+02:00
New Revision: 3eb4128eb0cb4a42b912ee352c120a9c0f2ddbd6
URL: https://github.com/llvm/llvm-project/commit/3eb4128eb0cb4a42b912ee352c120a9c0f2ddbd6
DIFF: https://github.com/llvm/llvm-project/commit/3eb4128eb0cb4a42b912ee352c120a9c0f2ddbd6.diff
LOG: [StackTagging] Generate test checks (NFC)
Added:
Modified:
llvm/test/CodeGen/AArch64/stack-tagging-initializer-merge.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/stack-tagging-initializer-merge.ll b/llvm/test/CodeGen/AArch64/stack-tagging-initializer-merge.ll
index 22d177ca3267e..cca1289708b5c 100644
--- a/llvm/test/CodeGen/AArch64/stack-tagging-initializer-merge.ll
+++ b/llvm/test/CodeGen/AArch64/stack-tagging-initializer-merge.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt < %s -aarch64-stack-tagging -S -o - | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
@@ -9,6 +10,19 @@ declare void @llvm.lifetime.end.p0(i64, ptr nocapture)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg)
define void @OneVarNoInit() sanitize_memtag {
+; CHECK-LABEL: define void @OneVarNoInit(
+; CHECK-SAME: ) #[[ATTR2:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[BASETAG:%.*]] = call ptr @llvm.aarch64.irg.sp(i64 0)
+; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
+; CHECK-NEXT: [[TX:%.*]] = call ptr @llvm.aarch64.tagp.p0(ptr [[X]], ptr [[BASETAG]], i64 0)
+; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr nonnull [[X]])
+; CHECK-NEXT: call void @llvm.aarch64.settag(ptr [[TX]], i64 16)
+; CHECK-NEXT: call void @use(ptr nonnull [[TX]])
+; CHECK-NEXT: call void @llvm.aarch64.settag(ptr [[X]], i64 16)
+; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr nonnull [[X]])
+; CHECK-NEXT: ret void
+;
entry:
%x = alloca i32, align 4
call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %x)
@@ -17,15 +31,21 @@ entry:
ret void
}
-; CHECK-LABEL: define void @OneVarNoInit(
-; CHECK-DAG: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
-; CHECK-DAG: [[TX:%.*]] = call ptr @llvm.aarch64.tagp.{{.*}}(ptr [[X]], {{.*}}, i64 0)
-; CHECK-DAG: call void @llvm.lifetime.start.p0(i64 4, ptr nonnull [[X]])
-; CHECK-DAG: call void @llvm.aarch64.settag(ptr [[TX]], i64 16)
-; CHECK-DAG: call void @use(ptr nonnull [[TX]])
-; CHECK-DAG: call void @llvm.lifetime.end.p0(i64 4, ptr nonnull [[X]])
define void @OneVarInitConst() sanitize_memtag {
+; CHECK-LABEL: define void @OneVarInitConst(
+; CHECK-SAME: ) #[[ATTR2]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[BASETAG:%.*]] = call ptr @llvm.aarch64.irg.sp(i64 0)
+; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
+; CHECK-NEXT: [[TX:%.*]] = call ptr @llvm.aarch64.tagp.p0(ptr [[X]], ptr [[BASETAG]], i64 0)
+; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr nonnull [[X]])
+; CHECK-NEXT: call void @llvm.aarch64.stgp(ptr [[TX]], i64 42, i64 0)
+; CHECK-NEXT: call void @use(ptr nonnull [[TX]])
+; CHECK-NEXT: call void @llvm.aarch64.settag(ptr [[X]], i64 16)
+; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr nonnull [[X]])
+; CHECK-NEXT: ret void
+;
entry:
%x = alloca i32, align 4
call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %x)
@@ -35,16 +55,24 @@ entry:
ret void
}
-; CHECK-LABEL: define void @OneVarInitConst(
-; CHECK: [[TX:%.*]] = call ptr @llvm.aarch64.tagp
-; CHECK-NOT: aarch64.settag
-; CHECK: call void @llvm.aarch64.stgp(ptr [[TX]], i64 42, i64 0)
; Untagging before lifetime.end:
-; CHECK: call void @llvm.aarch64.settag(
-; CHECK-NOT: aarch64.settag
-; CHECK: ret void
define void @ArrayInitConst() sanitize_memtag {
+; CHECK-LABEL: define void @ArrayInitConst(
+; CHECK-SAME: ) #[[ATTR2]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[BASETAG:%.*]] = call ptr @llvm.aarch64.irg.sp(i64 0)
+; CHECK-NEXT: [[X:%.*]] = alloca i32, i32 16, align 16
+; CHECK-NEXT: [[TX:%.*]] = call ptr @llvm.aarch64.tagp.p0(ptr [[X]], ptr [[BASETAG]], i64 0)
+; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 64, ptr nonnull [[X]])
+; CHECK-NEXT: call void @llvm.aarch64.stgp(ptr [[TX]], i64 42, i64 0)
+; CHECK-NEXT: [[TX8_16:%.*]] = getelementptr i8, ptr [[TX]], i32 16
+; CHECK-NEXT: call void @llvm.aarch64.settag.zero(ptr [[TX8_16]], i64 48)
+; CHECK-NEXT: call void @use(ptr nonnull [[TX]])
+; CHECK-NEXT: call void @llvm.aarch64.settag(ptr [[X]], i64 64)
+; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 64, ptr nonnull [[X]])
+; CHECK-NEXT: ret void
+;
entry:
%x = alloca i32, i32 16, align 4
call void @llvm.lifetime.start.p0(i64 64, ptr nonnull %x)
@@ -54,14 +82,25 @@ entry:
ret void
}
-; CHECK-LABEL: define void @ArrayInitConst(
-; CHECK: [[TX:%.*]] = call ptr @llvm.aarch64.tagp.
-; CHECK: call void @llvm.aarch64.stgp(ptr [[TX]], i64 42, i64 0)
-; CHECK: [[TX8_16:%.*]] = getelementptr i8, ptr [[TX]], i32 16
-; CHECK: call void @llvm.aarch64.settag.zero(ptr [[TX8_16]], i64 48)
-; CHECK: ret void
define void @ArrayInitConst2() sanitize_memtag {
+; CHECK-LABEL: define void @ArrayInitConst2(
+; CHECK-SAME: ) #[[ATTR2]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[BASETAG:%.*]] = call ptr @llvm.aarch64.irg.sp(i64 0)
+; CHECK-NEXT: [[X:%.*]] = alloca i32, i32 16, align 16
+; CHECK-NEXT: [[TX:%.*]] = call ptr @llvm.aarch64.tagp.p0(ptr [[X]], ptr [[BASETAG]], i64 0)
+; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 64, ptr nonnull [[X]])
+; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i32, ptr [[TX]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[TX]], i32 2
+; CHECK-NEXT: call void @llvm.aarch64.stgp(ptr [[TX]], i64 184683593770, i64 -1)
+; CHECK-NEXT: [[TX8_16:%.*]] = getelementptr i8, ptr [[TX]], i32 16
+; CHECK-NEXT: call void @llvm.aarch64.settag.zero(ptr [[TX8_16]], i64 48)
+; CHECK-NEXT: call void @use(ptr nonnull [[TX]])
+; CHECK-NEXT: call void @llvm.aarch64.settag(ptr [[X]], i64 64)
+; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 64, ptr nonnull [[X]])
+; CHECK-NEXT: ret void
+;
entry:
%x = alloca i32, i32 16, align 4
call void @llvm.lifetime.start.p0(i64 64, ptr nonnull %x)
@@ -75,14 +114,24 @@ entry:
ret void
}
-; CHECK-LABEL: define void @ArrayInitConst2(
-; CHECK: [[TX:%.*]] = call ptr @llvm.aarch64.tagp.
-; CHECK: call void @llvm.aarch64.stgp(ptr [[TX]], i64 184683593770, i64 -1)
-; CHECK: [[TX8_16:%.*]] = getelementptr i8, ptr [[TX]], i32 16
-; CHECK: call void @llvm.aarch64.settag.zero(ptr [[TX8_16]], i64 48)
-; CHECK: ret void
define void @ArrayInitConstSplit() sanitize_memtag {
+; CHECK-LABEL: define void @ArrayInitConstSplit(
+; CHECK-SAME: ) #[[ATTR2]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[BASETAG:%.*]] = call ptr @llvm.aarch64.irg.sp(i64 0)
+; CHECK-NEXT: [[X:%.*]] = alloca i32, i32 16, align 16
+; CHECK-NEXT: [[TX:%.*]] = call ptr @llvm.aarch64.tagp.p0(ptr [[X]], ptr [[BASETAG]], i64 0)
+; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 64, ptr nonnull [[X]])
+; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i32, ptr [[TX]], i32 1
+; CHECK-NEXT: call void @llvm.aarch64.stgp(ptr [[TX]], i64 -4294967296, i64 4294967295)
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TX]], i32 16
+; CHECK-NEXT: call void @llvm.aarch64.settag.zero(ptr [[TMP1]], i64 48)
+; CHECK-NEXT: call void @use(ptr nonnull [[TX]])
+; CHECK-NEXT: call void @llvm.aarch64.settag(ptr [[X]], i64 64)
+; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 64, ptr nonnull [[X]])
+; CHECK-NEXT: ret void
+;
entry:
%x = alloca i32, i32 16, align 4
call void @llvm.lifetime.start.p0(i64 64, ptr nonnull %x)
@@ -93,12 +142,31 @@ entry:
ret void
}
-; CHECK-LABEL: define void @ArrayInitConstSplit(
-; CHECK: [[TX:%.*]] = call ptr @llvm.aarch64.tagp.
-; CHECK: call void @llvm.aarch64.stgp(ptr [[TX]], i64 -4294967296, i64 4294967295)
-; CHECK: ret void
define void @ArrayInitConstWithHoles() sanitize_memtag {
+; CHECK-LABEL: define void @ArrayInitConstWithHoles(
+; CHECK-SAME: ) #[[ATTR2]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[BASETAG:%.*]] = call ptr @llvm.aarch64.irg.sp(i64 0)
+; CHECK-NEXT: [[X:%.*]] = alloca i32, i32 32, align 16
+; CHECK-NEXT: [[TX:%.*]] = call ptr @llvm.aarch64.tagp.p0(ptr [[X]], ptr [[BASETAG]], i64 0)
+; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 128, ptr nonnull [[X]])
+; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i32, ptr [[TX]], i32 5
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[TX]], i32 14
+; CHECK-NEXT: call void @llvm.aarch64.settag.zero(ptr [[TX]], i64 16)
+; CHECK-NEXT: [[TX8_16:%.*]] = getelementptr i8, ptr [[TX]], i32 16
+; CHECK-NEXT: call void @llvm.aarch64.stgp(ptr [[TX8_16]], i64 180388626432, i64 0)
+; CHECK-NEXT: [[TX8_32:%.*]] = getelementptr i8, ptr [[TX]], i32 32
+; CHECK-NEXT: call void @llvm.aarch64.settag.zero(ptr [[TX8_32]], i64 16)
+; CHECK-NEXT: [[TX8_48:%.*]] = getelementptr i8, ptr [[TX]], i32 48
+; CHECK-NEXT: call void @llvm.aarch64.stgp(ptr [[TX8_48]], i64 0, i64 43)
+; CHECK-NEXT: [[TX8_64:%.*]] = getelementptr i8, ptr [[TX]], i32 64
+; CHECK-NEXT: call void @llvm.aarch64.settag.zero(ptr [[TX8_64]], i64 64)
+; CHECK-NEXT: call void @use(ptr nonnull [[TX]])
+; CHECK-NEXT: call void @llvm.aarch64.settag(ptr [[X]], i64 128)
+; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 128, ptr nonnull [[X]])
+; CHECK-NEXT: ret void
+;
entry:
%x = alloca i32, i32 32, align 4
call void @llvm.lifetime.start.p0(i64 128, ptr nonnull %x)
@@ -111,20 +179,22 @@ entry:
ret void
}
-; CHECK-LABEL: define void @ArrayInitConstWithHoles(
-; CHECK: [[TX:%.*]] = call ptr @llvm.aarch64.tagp.
-; CHECK: call void @llvm.aarch64.settag.zero(ptr [[TX]], i64 16)
-; CHECK: [[TX8_16:%.*]] = getelementptr i8, ptr %x.tag, i32 16
-; CHECK: call void @llvm.aarch64.stgp(ptr [[TX8_16]], i64 180388626432, i64 0)
-; CHECK: [[TX8_32:%.*]] = getelementptr i8, ptr %x.tag, i32 32
-; CHECK: call void @llvm.aarch64.settag.zero(ptr [[TX8_32]], i64 16)
-; CHECK: [[TX8_48:%.*]] = getelementptr i8, ptr %x.tag, i32 48
-; CHECK: call void @llvm.aarch64.stgp(ptr [[TX8_48]], i64 0, i64 43)
-; CHECK: [[TX8_64:%.*]] = getelementptr i8, ptr %x.tag, i32 64
-; CHECK: call void @llvm.aarch64.settag.zero(ptr [[TX8_64]], i64 64)
-; CHECK: ret void
define void @InitNonConst(i32 %v) sanitize_memtag {
+; CHECK-LABEL: define void @InitNonConst(
+; CHECK-SAME: i32 [[V:%.*]]) #[[ATTR2]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[BASETAG:%.*]] = call ptr @llvm.aarch64.irg.sp(i64 0)
+; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
+; CHECK-NEXT: [[X_TAG:%.*]] = call ptr @llvm.aarch64.tagp.p0(ptr [[X]], ptr [[BASETAG]], i64 0)
+; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr nonnull [[X]])
+; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[V]] to i64
+; CHECK-NEXT: call void @llvm.aarch64.stgp(ptr [[X_TAG]], i64 [[TMP0]], i64 0)
+; CHECK-NEXT: call void @use(ptr nonnull [[X_TAG]])
+; CHECK-NEXT: call void @llvm.aarch64.settag(ptr [[X]], i64 16)
+; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr nonnull [[X]])
+; CHECK-NEXT: ret void
+;
entry:
%x = alloca i32, align 4
call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %x)
@@ -134,13 +204,26 @@ entry:
ret void
}
-; CHECK-LABEL: define void @InitNonConst(
-; CHECK: [[TX:%.*]] = call ptr @llvm.aarch64.tagp
-; CHECK: [[V:%.*]] = zext i32 %v to i64
-; CHECK: call void @llvm.aarch64.stgp(ptr [[TX]], i64 [[V]], i64 0)
-; CHECK: ret void
define void @InitNonConst2(i32 %v, i32 %w) sanitize_memtag {
+; CHECK-LABEL: define void @InitNonConst2(
+; CHECK-SAME: i32 [[V:%.*]], i32 [[W:%.*]]) #[[ATTR2]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[BASETAG:%.*]] = call ptr @llvm.aarch64.irg.sp(i64 0)
+; CHECK-NEXT: [[X:%.*]] = alloca i32, i32 4, align 16
+; CHECK-NEXT: [[TX:%.*]] = call ptr @llvm.aarch64.tagp.p0(ptr [[X]], ptr [[BASETAG]], i64 0)
+; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[X]])
+; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[V]] to i64
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[TX]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[W]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 32
+; CHECK-NEXT: [[VW:%.*]] = or i64 [[TMP0]], [[TMP3]]
+; CHECK-NEXT: call void @llvm.aarch64.stgp(ptr [[TX]], i64 [[VW]], i64 0)
+; CHECK-NEXT: call void @use(ptr nonnull [[TX]])
+; CHECK-NEXT: call void @llvm.aarch64.settag(ptr [[X]], i64 16)
+; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[X]])
+; CHECK-NEXT: ret void
+;
entry:
%x = alloca i32, i32 4, align 4
call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %x)
@@ -152,16 +235,21 @@ entry:
ret void
}
-; CHECK-LABEL: define void @InitNonConst2(
-; CHECK: [[TX:%.*]] = call ptr @llvm.aarch64.tagp
-; CHECK: [[V:%.*]] = zext i32 %v to i64
-; CHECK: [[W:%.*]] = zext i32 %w to i64
-; CHECK: [[WS:%.*]] = shl i64 [[W]], 32
-; CHECK: [[VW:%.*]] = or i64 [[V]], [[WS]]
-; CHECK: call void @llvm.aarch64.stgp(ptr [[TX]], i64 [[VW]], i64 0)
-; CHECK: ret void
define void @InitVector() sanitize_memtag {
+; CHECK-LABEL: define void @InitVector(
+; CHECK-SAME: ) #[[ATTR2]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[BASETAG:%.*]] = call ptr @llvm.aarch64.irg.sp(i64 0)
+; CHECK-NEXT: [[X:%.*]] = alloca i32, i32 4, align 16
+; CHECK-NEXT: [[TX:%.*]] = call ptr @llvm.aarch64.tagp.p0(ptr [[X]], ptr [[BASETAG]], i64 0)
+; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[X]])
+; CHECK-NEXT: call void @llvm.aarch64.stgp(ptr [[TX]], i64 bitcast (<2 x i32> <i32 1, i32 2> to i64), i64 0)
+; CHECK-NEXT: call void @use(ptr nonnull [[TX]])
+; CHECK-NEXT: call void @llvm.aarch64.settag(ptr [[X]], i64 16)
+; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[X]])
+; CHECK-NEXT: ret void
+;
entry:
%x = alloca i32, i32 4, align 4
call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %x)
@@ -171,12 +259,32 @@ entry:
ret void
}
-; CHECK-LABEL: define void @InitVector(
-; CHECK: [[TX:%.*]] = call ptr @llvm.aarch64.tagp
-; CHECK: call void @llvm.aarch64.stgp(ptr [[TX]], i64 bitcast (<2 x i32> <i32 1, i32 2> to i64), i64 0)
-; CHECK: ret void
define void @InitVectorPtr(ptr %p) sanitize_memtag {
+; CHECK-LABEL: define void @InitVectorPtr(
+; CHECK-SAME: ptr [[P:%.*]]) #[[ATTR2]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[BASETAG:%.*]] = call ptr @llvm.aarch64.irg.sp(i64 0)
+; CHECK-NEXT: [[S:%.*]] = alloca <4 x ptr>, align 16
+; CHECK-NEXT: [[S_TAG:%.*]] = call ptr @llvm.aarch64.tagp.p0(ptr [[S]], ptr [[BASETAG]], i64 0)
+; CHECK-NEXT: [[V0:%.*]] = insertelement <4 x ptr> undef, ptr [[P]], i32 0
+; CHECK-NEXT: [[V1:%.*]] = shufflevector <4 x ptr> [[V0]], <4 x ptr> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT: [[V2:%.*]] = ptrtoint <4 x ptr> [[V1]] to <4 x i64>
+; CHECK-NEXT: [[V3:%.*]] = bitcast <4 x i64> [[V2]] to i256
+; CHECK-NEXT: [[A1:%.*]] = trunc i256 [[V3]] to i64
+; CHECK-NEXT: [[A2_:%.*]] = lshr i256 [[V3]], 64
+; CHECK-NEXT: [[A2:%.*]] = trunc i256 [[A2_]] to i64
+; CHECK-NEXT: [[A3_:%.*]] = lshr i256 [[V3]], 128
+; CHECK-NEXT: [[A3:%.*]] = trunc i256 [[A3_]] to i64
+; CHECK-NEXT: [[A4_:%.*]] = lshr i256 [[V3]], 192
+; CHECK-NEXT: [[A4:%.*]] = trunc i256 [[A4_]] to i64
+; CHECK-NEXT: call void @llvm.aarch64.stgp(ptr [[S_TAG]], i64 [[A1]], i64 [[A2]])
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[S_TAG]], i32 16
+; CHECK-NEXT: call void @llvm.aarch64.stgp(ptr [[TMP9]], i64 [[A3]], i64 [[A4]])
+; CHECK-NEXT: call void @use(ptr nonnull [[S_TAG]])
+; CHECK-NEXT: call void @llvm.aarch64.settag(ptr [[S]], i64 32)
+; CHECK-NEXT: ret void
+;
entry:
%s = alloca <4 x ptr>, align 8
%v0 = insertelement <4 x ptr> undef, ptr %p, i32 0
@@ -186,23 +294,23 @@ entry:
ret void
}
-; CHECK-LABEL: define void @InitVectorPtr(
-; CHECK: call ptr @llvm.aarch64.tagp
-; CHECK: [[V1:%.*]] = shufflevector
-; CHECK: [[V2:%.*]] = ptrtoint <4 x ptr> [[V1]] to <4 x i64>
-; CHECK: [[V3:%.*]] = bitcast <4 x i64> [[V2]] to i256
-; CHECK: [[A1:%.*]] = trunc i256 [[V3]] to i64
-; CHECK: [[A2_:%.*]] = lshr i256 [[V3]], 64
-; CHECK: [[A2:%.*]] = trunc i256 [[A2_]] to i64
-; CHECK: [[A3_:%.*]] = lshr i256 [[V3]], 128
-; CHECK: [[A3:%.*]] = trunc i256 [[A3_]] to i64
-; CHECK: [[A4_:%.*]] = lshr i256 [[V3]], 192
-; CHECK: [[A4:%.*]] = trunc i256 [[A4_]] to i64
-; CHECK: call void @llvm.aarch64.stgp({{.*}}, i64 [[A1]], i64 [[A2]])
-; CHECK: call void @llvm.aarch64.stgp({{.*}}, i64 [[A3]], i64 [[A4]])
-; CHECK: ret void
define void @InitVectorSplit() sanitize_memtag {
+; CHECK-LABEL: define void @InitVectorSplit(
+; CHECK-SAME: ) #[[ATTR2]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[BASETAG:%.*]] = call ptr @llvm.aarch64.irg.sp(i64 0)
+; CHECK-NEXT: [[X:%.*]] = alloca i32, i32 4, align 16
+; CHECK-NEXT: [[TX:%.*]] = call ptr @llvm.aarch64.tagp.p0(ptr [[X]], ptr [[BASETAG]], i64 0)
+; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[X]])
+; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i32, ptr [[TX]], i32 1
+; CHECK-NEXT: [[LSHR:%.*]] = lshr i64 bitcast (<2 x i32> <i32 1, i32 2> to i64), 32
+; CHECK-NEXT: call void @llvm.aarch64.stgp(ptr [[TX]], i64 shl (i64 bitcast (<2 x i32> <i32 1, i32 2> to i64), i64 32), i64 [[LSHR]])
+; CHECK-NEXT: call void @use(ptr nonnull [[TX]])
+; CHECK-NEXT: call void @llvm.aarch64.settag(ptr [[X]], i64 16)
+; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[X]])
+; CHECK-NEXT: ret void
+;
entry:
%x = alloca i32, i32 4, align 4
call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %x)
@@ -213,13 +321,19 @@ entry:
ret void
}
-; CHECK-LABEL: define void @InitVectorSplit(
-; CHECK: [[TX:%.*]] = call ptr @llvm.aarch64.tagp
-; CHECK: [[LSHR:%.*]] = lshr i64 bitcast (<2 x i32> <i32 1, i32 2> to i64), 32
-; CHECK: call void @llvm.aarch64.stgp(ptr [[TX]], i64 shl (i64 bitcast (<2 x i32> <i32 1, i32 2> to i64), i64 32), i64 [[LSHR]])
-; CHECK: ret void
define void @MemSetZero() sanitize_memtag {
+; CHECK-LABEL: define void @MemSetZero(
+; CHECK-SAME: ) #[[ATTR2]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[BASETAG:%.*]] = call ptr @llvm.aarch64.irg.sp(i64 0)
+; CHECK-NEXT: [[X:%.*]] = alloca i32, i32 8, align 16
+; CHECK-NEXT: [[TX:%.*]] = call ptr @llvm.aarch64.tagp.p0(ptr [[X]], ptr [[BASETAG]], i64 0)
+; CHECK-NEXT: call void @llvm.aarch64.settag.zero(ptr [[TX]], i64 32)
+; CHECK-NEXT: call void @use(ptr nonnull [[TX]])
+; CHECK-NEXT: call void @llvm.aarch64.settag(ptr [[X]], i64 32)
+; CHECK-NEXT: ret void
+;
entry:
%x = alloca i32, i32 8, align 16
call void @llvm.memset.p0.i64(ptr nonnull align 16 %x, i8 0, i64 32, i1 false)
@@ -227,13 +341,22 @@ entry:
ret void
}
-; CHECK-LABEL: define void @MemSetZero(
-; CHECK: [[TX:%.*]] = call ptr @llvm.aarch64.tagp
-; CHECK: call void @llvm.aarch64.settag.zero(ptr [[TX]], i64 32)
-; CHECK: ret void
define void @MemSetNonZero() sanitize_memtag {
+; CHECK-LABEL: define void @MemSetNonZero(
+; CHECK-SAME: ) #[[ATTR2]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[BASETAG:%.*]] = call ptr @llvm.aarch64.irg.sp(i64 0)
+; CHECK-NEXT: [[X:%.*]] = alloca i32, i32 8, align 16
+; CHECK-NEXT: [[X_TAG:%.*]] = call ptr @llvm.aarch64.tagp.p0(ptr [[X]], ptr [[BASETAG]], i64 0)
+; CHECK-NEXT: call void @llvm.aarch64.stgp(ptr [[X_TAG]], i64 3038287259199220266, i64 3038287259199220266)
+; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[X_TAG]], i32 16
+; CHECK-NEXT: call void @llvm.aarch64.stgp(ptr [[TMP0]], i64 3038287259199220266, i64 3038287259199220266)
+; CHECK-NEXT: call void @use(ptr nonnull [[X_TAG]])
+; CHECK-NEXT: call void @llvm.aarch64.settag(ptr [[X]], i64 32)
+; CHECK-NEXT: ret void
+;
entry:
%x = alloca i32, i32 8, align 16
call void @llvm.memset.p0.i64(ptr nonnull align 16 %x, i8 42, i64 32, i1 false)
@@ -241,13 +364,23 @@ entry:
ret void
}
-; CHECK-LABEL: define void @MemSetNonZero(
-; CHECK: call void @llvm.aarch64.stgp(ptr {{.*}}, i64 3038287259199220266, i64 3038287259199220266)
-; CHECK: call void @llvm.aarch64.stgp(ptr {{.*}}, i64 3038287259199220266, i64 3038287259199220266)
-; CHECK: ret void
define void @MemSetNonZero2() sanitize_memtag {
+; CHECK-LABEL: define void @MemSetNonZero2(
+; CHECK-SAME: ) #[[ATTR2]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[BASETAG:%.*]] = call ptr @llvm.aarch64.irg.sp(i64 0)
+; CHECK-NEXT: [[X:%.*]] = alloca [32 x i8], align 16
+; CHECK-NEXT: [[X_TAG:%.*]] = call ptr @llvm.aarch64.tagp.p0(ptr [[X]], ptr [[BASETAG]], i64 0)
+; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds [32 x i8], ptr [[X_TAG]], i64 0, i64 2
+; CHECK-NEXT: call void @llvm.aarch64.stgp(ptr [[X_TAG]], i64 3038287259199209472, i64 3038287259199220266)
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[X_TAG]], i32 16
+; CHECK-NEXT: call void @llvm.aarch64.stgp(ptr [[TMP1]], i64 3038287259199220266, i64 46360584399402)
+; CHECK-NEXT: call void @use(ptr nonnull [[TMP0]])
+; CHECK-NEXT: call void @llvm.aarch64.settag(ptr [[X]], i64 32)
+; CHECK-NEXT: ret void
+;
entry:
%x = alloca [32 x i8], align 16
%0 = getelementptr inbounds [32 x i8], ptr %x, i64 0, i64 2
@@ -256,12 +389,23 @@ entry:
ret void
}
-; CHECK-LABEL: define void @MemSetNonZero2(
-; CHECK: call void @llvm.aarch64.stgp(ptr {{.*}}, i64 3038287259199209472, i64 3038287259199220266)
-; CHECK: call void @llvm.aarch64.stgp(ptr {{.*}}, i64 3038287259199220266, i64 46360584399402)
-; CHECK: ret void
define void @MemSetNonZero3() sanitize_memtag {
+; CHECK-LABEL: define void @MemSetNonZero3(
+; CHECK-SAME: ) #[[ATTR2]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[BASETAG:%.*]] = call ptr @llvm.aarch64.irg.sp(i64 0)
+; CHECK-NEXT: [[X:%.*]] = alloca [32 x i8], align 16
+; CHECK-NEXT: [[X_TAG:%.*]] = call ptr @llvm.aarch64.tagp.p0(ptr [[X]], ptr [[BASETAG]], i64 0)
+; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds [32 x i8], ptr [[X_TAG]], i64 0, i64 2
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [32 x i8], ptr [[X_TAG]], i64 0, i64 24
+; CHECK-NEXT: call void @llvm.aarch64.stgp(ptr [[X_TAG]], i64 46360584388608, i64 0)
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[X_TAG]], i32 16
+; CHECK-NEXT: call void @llvm.aarch64.stgp(ptr [[TMP2]], i64 0, i64 3038287259199220266)
+; CHECK-NEXT: call void @use(ptr nonnull [[TMP0]])
+; CHECK-NEXT: call void @llvm.aarch64.settag(ptr [[X]], i64 32)
+; CHECK-NEXT: ret void
+;
entry:
%x = alloca [32 x i8], align 16
%0 = getelementptr inbounds [32 x i8], ptr %x, i64 0, i64 2
@@ -272,12 +416,20 @@ entry:
ret void
}
-; CHECK-LABEL: define void @MemSetNonZero3(
-; CHECK: call void @llvm.aarch64.stgp(ptr {{.*}}, i64 46360584388608, i64 0)
-; CHECK: call void @llvm.aarch64.stgp(ptr {{.*}}, i64 0, i64 3038287259199220266)
-; CHECK: ret void
define void @LargeAlloca() sanitize_memtag {
+; CHECK-LABEL: define void @LargeAlloca(
+; CHECK-SAME: ) #[[ATTR2]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[BASETAG:%.*]] = call ptr @llvm.aarch64.irg.sp(i64 0)
+; CHECK-NEXT: [[X:%.*]] = alloca i32, i32 256, align 16
+; CHECK-NEXT: [[X_TAG:%.*]] = call ptr @llvm.aarch64.tagp.p0(ptr [[X]], ptr [[BASETAG]], i64 0)
+; CHECK-NEXT: call void @llvm.aarch64.settag(ptr [[X_TAG]], i64 1024)
+; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr nonnull align 16 [[X_TAG]], i8 42, i64 256, i1 false)
+; CHECK-NEXT: call void @use(ptr nonnull [[X_TAG]])
+; CHECK-NEXT: call void @llvm.aarch64.settag(ptr [[X]], i64 1024)
+; CHECK-NEXT: ret void
+;
entry:
%x = alloca i32, i32 256, align 16
call void @llvm.memset.p0.i64(ptr nonnull align 16 %x, i8 42, i64 256, i1 false)
@@ -285,7 +437,3 @@ entry:
ret void
}
-; CHECK-LABEL: define void @LargeAlloca(
-; CHECK: call void @llvm.aarch64.settag(ptr {{.*}}, i64 1024)
-; CHECK: call void @llvm.memset.p0.i64(ptr {{.*}}, i8 42, i64 256,
-; CHECK: ret void
More information about the llvm-commits
mailing list