[llvm] 6be6c3a - [InstCombine] Use disjoint flag for alternate binops

[Nikita Popov via llvm-commits]

Author: Nikita Popov
Date: 2024-06-18T16:51:37+02:00
New Revision: 6be6c3a37be46ebefa967b66e398d8ea9ed4ffe8

URL: https://github.com/llvm/llvm-project/commit/6be6c3a37be46ebefa967b66e398d8ea9ed4ffe8
DIFF: https://github.com/llvm/llvm-project/commit/6be6c3a37be46ebefa967b66e398d8ea9ed4ffe8.diff

LOG: [InstCombine] Use disjoint flag for alternate binops

Check the or disjoint flag instead of the weaker MaskedValueIsZero
query.

Added: 
    

Modified: 
    llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
    llvm/test/Transforms/InstCombine/shuffle_select.ll

Removed: 
    


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diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
index 5e3f659240edd..ebc2930d33d26 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
@@ -2072,9 +2072,8 @@ static BinopElts getAlternateBinop(BinaryOperator *BO, const DataLayout &DL) {
     break;
   }
   case Instruction::Or: {
-    // or X, C --> add X, C (when X and C have no common bits set)
-    const APInt *C;
-    if (match(BO1, m_APInt(C)) && MaskedValueIsZero(BO0, *C, DL))
+    // or disjoin X, C --> add X, C
+    if (cast<PossiblyDisjointInst>(BO)->isDisjoint())
       return {Instruction::Add, BO0, BO1};
     break;
   }

diff  --git a/llvm/test/Transforms/InstCombine/shuffle_select.ll b/llvm/test/Transforms/InstCombine/shuffle_select.ll
index efadb5c3c1094..7516ea5c0a42c 100644
--- a/llvm/test/Transforms/InstCombine/shuffle_select.ll
+++ b/llvm/test/Transforms/InstCombine/shuffle_select.ll
@@ -1466,6 +1466,17 @@ define <4 x i32> @add_or(<4 x i32> %v) {
   ret <4 x i32> %t3
 }
 
+define <4 x i32> @add_or_disjoint(<4 x i32> %v) {
+; CHECK-LABEL: @add_or_disjoint(
+; CHECK-NEXT:    [[T3:%.*]] = add <4 x i32> [[V:%.*]], <i32 31, i32 31, i32 65536, i32 65537>
+; CHECK-NEXT:    ret <4 x i32> [[T3]]
+;
+  %t1 = add <4 x i32> %v, <i32 65534, i32 65535, i32 65536, i32 65537>
+  %t2 = or disjoint <4 x i32> %v, <i32 31, i32 31, i32 31, i32 31>
+  %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
+  ret <4 x i32> %t3
+}
+
 ; Try with 'or' as operand 0 of the shuffle.
 
 define <4 x i8> @or_add(<4 x i8> %v) {