[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

[Craig Topper via llvm-commits]

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@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtHFusion,
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
+                                       NoSchedModel,
+                                       !listconcat(RVA22S64Features,
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topperc wrote:

Need to add `Feature64Bit` and maybe others

https://github.com/llvm/llvm-project/pull/94564