[llvm] [NFC][NVPTX][test] Update test for `fneg half` (PR #95856)

[Justin Fargnoli via llvm-commits]

https://github.com/justinfargnoli updated https://github.com/llvm/llvm-project/pull/95856

>From 5c1da54d8292a1edd3bc0f81faa37b9dc5779b9c Mon Sep 17 00:00:00 2001
From: Justin Fargnoli <jfargnoli at nvidia.com>
Date: Mon, 17 Jun 2024 15:01:48 -0700
Subject: [PATCH 1/2] [NFC][NVPTX][test] Update test for `fneg half`

---
 llvm/test/CodeGen/NVPTX/f16-instructions.ll | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/llvm/test/CodeGen/NVPTX/f16-instructions.ll b/llvm/test/CodeGen/NVPTX/f16-instructions.ll
index deea2e3b557f1..e1c50b3982417 100644
--- a/llvm/test/CodeGen/NVPTX/f16-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/f16-instructions.ll
@@ -131,8 +131,8 @@ define half @test_fsub(half %a, half %b) #0 {
   ret half %r
 }
 
-; CHECK-LABEL: test_fneg(
-; CHECK-DAG:  ld.param.b16    [[A:%rs[0-9]+]], [test_fneg_param_0];
+; CHECK-LABEL: test_old_fneg(
+; CHECK-DAG:  ld.param.b16    [[A:%rs[0-9]+]], [test_old_fneg_param_0];
 ; CHECK-F16-NOFTZ-NEXT:   mov.b16        [[Z:%rs[0-9]+]], 0x0000
 ; CHECK-F16-NOFTZ-NEXT:   sub.rn.f16     [[R:%rs[0-9]+]], [[Z]], [[A]];
 ; CHECK-F16-FTZ-NEXT:   mov.b16        [[Z:%rs[0-9]+]], 0x0000
@@ -143,11 +143,21 @@ define half @test_fsub(half %a, half %b) #0 {
 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%rs[0-9]+]], [[R32]]
 ; CHECK-NEXT: st.param.b16    [func_retval0+0], [[R]];
 ; CHECK-NEXT: ret;
-define half @test_fneg(half %a) #0 {
+define half @test_old_fneg(half %a) #0 {
   %r = fsub half 0.0, %a
   ret half %r
 }
 
+; CHECK-LABEL: test_fneg(
+; CHECK-DAG:  ld.param.b16    [[A:%rs[0-9]+]], [test_fneg_param_0];
+; CHECK-NEXT: xor.b16    [[R:%rs[0-9]+]], [[A]], -32768;
+; CHECK-NEXT: st.param.b16    [func_retval0+0], [[R]];
+; CHECK-NEXT: ret;
+define half @test_fneg(half %a) #0 {
+  %r = fneg half %a
+  ret half %r
+}
+
 ; CHECK-LABEL: test_fmul(
 ; CHECK-DAG:  ld.param.b16    [[A:%rs[0-9]+]], [test_fmul_param_0];
 ; CHECK-DAG:  ld.param.b16    [[B:%rs[0-9]+]], [test_fmul_param_1];

>From 5da6544f33a3b7822eab0889cbd06a793481089f Mon Sep 17 00:00:00 2001
From: Justin Fargnoli <jfargnoli at nvidia.com>
Date: Mon, 17 Jun 2024 15:39:25 -0700
Subject: [PATCH 2/2] Update tests

---
 llvm/test/CodeGen/NVPTX/f16-instructions.ll | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/llvm/test/CodeGen/NVPTX/f16-instructions.ll b/llvm/test/CodeGen/NVPTX/f16-instructions.ll
index e1c50b3982417..234da13f7e3a5 100644
--- a/llvm/test/CodeGen/NVPTX/f16-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/f16-instructions.ll
@@ -149,8 +149,10 @@ define half @test_old_fneg(half %a) #0 {
 }
 
 ; CHECK-LABEL: test_fneg(
-; CHECK-DAG:  ld.param.b16    [[A:%rs[0-9]+]], [test_fneg_param_0];
-; CHECK-NEXT: xor.b16    [[R:%rs[0-9]+]], [[A]], -32768;
+; CHECK:  ld.param.b16    [[A:%rs[0-9]+]], [test_fneg_param_0];
+; CHECK-F16-NOFTZ-NEXT:   neg.f16     [[R:%rs[0-9]+]], [[A]];
+; CHECK-F16-FTZ-NEXT:   neg.ftz.f16     [[R:%rs[0-9]+]], [[A]];
+; CHECK-NOF16-NEXT:  xor.b16    [[R:%rs[0-9]+]], [[A]], -32768;
 ; CHECK-NEXT: st.param.b16    [func_retval0+0], [[R]];
 ; CHECK-NEXT: ret;
 define half @test_fneg(half %a) #0 {