[llvm] 1d02815 - Revert "[RISCV] Teach RISCVInsertVSETVLI to work without LiveIntervals (#94686)"
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 17 12:05:12 PDT 2024
Author: Philip Reames
Date: 2024-06-17T12:04:44-07:00
New Revision: 1d028151c9cd79d76c1cda0bc3b4f10a2239d8b6
URL: https://github.com/llvm/llvm-project/commit/1d028151c9cd79d76c1cda0bc3b4f10a2239d8b6
DIFF: https://github.com/llvm/llvm-project/commit/1d028151c9cd79d76c1cda0bc3b4f10a2239d8b6.diff
LOG: Revert "[RISCV] Teach RISCVInsertVSETVLI to work without LiveIntervals (#94686)"
This reverts commit 111507ed4ce49bbb8cfbf36a3e143bb25f0f13c0. Accidentally landed with stale commit message, will reply shortly.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/test/CodeGen/RISCV/O0-pipeline.ll
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-O0.ll
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
Removed:
llvm/test/CodeGen/RISCV/rvv/pr93587.ll
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index b7dad160a7f64..151a7821f835d 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -48,13 +48,10 @@ static cl::opt<bool> DisableInsertVSETVLPHIOpt(
namespace {
/// Given a virtual register \p Reg, return the corresponding VNInfo for it.
-/// This will return nullptr if the virtual register is an implicit_def or
-/// if LiveIntervals is not available.
+/// This will return nullptr if the virtual register is an implicit_def.
static VNInfo *getVNInfoFromReg(Register Reg, const MachineInstr &MI,
const LiveIntervals *LIS) {
assert(Reg.isVirtual());
- if (!LIS)
- return nullptr;
auto &LI = LIS->getInterval(Reg);
SlotIndex SI = LIS->getSlotIndexes()->getInstructionIndex(MI);
return LI.getVNInfoBefore(SI);
@@ -515,8 +512,7 @@ DemandedFields getDemanded(const MachineInstr &MI, const RISCVSubtarget *ST) {
/// values of the VL and VTYPE registers after insertion.
class VSETVLIInfo {
struct AVLDef {
- // Every AVLDef should have a VNInfo, unless we're running without
- // LiveIntervals in which case this will be nullptr.
+ // Every AVLDef should have a VNInfo.
const VNInfo *ValNo;
Register DefReg;
};
@@ -530,7 +526,7 @@ class VSETVLIInfo {
AVLIsReg,
AVLIsImm,
AVLIsVLMAX,
- Unknown, // AVL and VTYPE are fully unknown
+ Unknown,
} State = Uninitialized;
// Fields from VTYPE.
@@ -556,7 +552,7 @@ class VSETVLIInfo {
bool isUnknown() const { return State == Unknown; }
void setAVLRegDef(const VNInfo *VNInfo, Register AVLReg) {
- assert(AVLReg.isVirtual());
+ assert(VNInfo && AVLReg.isVirtual());
AVLRegDef.ValNo = VNInfo;
AVLRegDef.DefReg = AVLReg;
State = AVLIsReg;
@@ -586,11 +582,9 @@ class VSETVLIInfo {
}
// Most AVLIsReg infos will have a single defining MachineInstr, unless it was
// a PHI node. In that case getAVLVNInfo()->def will point to the block
- // boundary slot. If LiveIntervals isn't available, then nullptr is returned.
+ // boundary slot.
const MachineInstr *getAVLDefMI(const LiveIntervals *LIS) const {
assert(hasAVLReg());
- if (!LIS)
- return nullptr;
auto *MI = LIS->getInstructionFromIndex(getAVLVNInfo()->def);
assert(!(getAVLVNInfo()->isPHIDef() && MI));
return MI;
@@ -634,15 +628,10 @@ class VSETVLIInfo {
return (hasNonZeroAVL(LIS) && Other.hasNonZeroAVL(LIS));
}
- bool hasSameAVLLatticeValue(const VSETVLIInfo &Other) const {
- if (hasAVLReg() && Other.hasAVLReg()) {
- assert(!getAVLVNInfo() == !Other.getAVLVNInfo() &&
- "we either have intervals or we don't");
- if (!getAVLVNInfo())
- return getAVLReg() == Other.getAVLReg();
+ bool hasSameAVL(const VSETVLIInfo &Other) const {
+ if (hasAVLReg() && Other.hasAVLReg())
return getAVLVNInfo()->id == Other.getAVLVNInfo()->id &&
getAVLReg() == Other.getAVLReg();
- }
if (hasAVLImm() && Other.hasAVLImm())
return getAVLImm() == Other.getAVLImm();
@@ -653,21 +642,6 @@ class VSETVLIInfo {
return false;
}
- // Return true if the two lattice values are guaranteed to have
- // the same AVL value at runtime.
- bool hasSameAVL(const VSETVLIInfo &Other) const {
- // Without LiveIntervals, we don't know which instruction defines a
- // register. Since a register may be redefined, this means all AVLIsReg
- // states must be treated as possibly distinct.
- if (hasAVLReg() && Other.hasAVLReg()) {
- assert(!getAVLVNInfo() == !Other.getAVLVNInfo() &&
- "we either have intervals or we don't");
- if (!getAVLVNInfo())
- return false;
- }
- return hasSameAVLLatticeValue(Other);
- }
-
void setVTYPE(unsigned VType) {
assert(isValid() && !isUnknown() &&
"Can't set VTYPE for uninitialized or unknown");
@@ -767,7 +741,7 @@ class VSETVLIInfo {
if (Other.isUnknown())
return isUnknown();
- if (!hasSameAVLLatticeValue(Other))
+ if (!hasSameAVL(Other))
return false;
// If the SEWLMULRatioOnly bits are
diff erent, then they aren't equal.
@@ -875,7 +849,6 @@ class RISCVInsertVSETVLI : public MachineFunctionPass {
const RISCVSubtarget *ST;
const TargetInstrInfo *TII;
MachineRegisterInfo *MRI;
- // Possibly null!
LiveIntervals *LIS;
std::vector<BlockData> BlockInfo;
@@ -890,9 +863,9 @@ class RISCVInsertVSETVLI : public MachineFunctionPass {
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG();
- AU.addUsedIfAvailable<LiveIntervals>();
+ AU.addRequired<LiveIntervals>();
AU.addPreserved<LiveIntervals>();
- AU.addUsedIfAvailable<SlotIndexes>();
+ AU.addRequired<SlotIndexes>();
AU.addPreserved<SlotIndexes>();
AU.addPreserved<LiveDebugVariables>();
AU.addPreserved<LiveStacks>();
@@ -1088,8 +1061,7 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
.addReg(RISCV::X0, RegState::Kill)
.addImm(Info.encodeVTYPE())
.addReg(RISCV::VL, RegState::Implicit);
- if (LIS)
- LIS->InsertMachineInstrInMaps(*MI);
+ LIS->InsertMachineInstrInMaps(*MI);
return;
}
@@ -1106,8 +1078,7 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
.addReg(RISCV::X0, RegState::Kill)
.addImm(Info.encodeVTYPE())
.addReg(RISCV::VL, RegState::Implicit);
- if (LIS)
- LIS->InsertMachineInstrInMaps(*MI);
+ LIS->InsertMachineInstrInMaps(*MI);
return;
}
}
@@ -1119,8 +1090,7 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
.addReg(RISCV::X0, RegState::Define | RegState::Dead)
.addImm(Info.getAVLImm())
.addImm(Info.encodeVTYPE());
- if (LIS)
- LIS->InsertMachineInstrInMaps(*MI);
+ LIS->InsertMachineInstrInMaps(*MI);
return;
}
@@ -1130,10 +1100,8 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
.addReg(DestReg, RegState::Define | RegState::Dead)
.addReg(RISCV::X0, RegState::Kill)
.addImm(Info.encodeVTYPE());
- if (LIS) {
- LIS->InsertMachineInstrInMaps(*MI);
- LIS->createAndComputeVirtRegInterval(DestReg);
- }
+ LIS->InsertMachineInstrInMaps(*MI);
+ LIS->createAndComputeVirtRegInterval(DestReg);
return;
}
@@ -1143,14 +1111,12 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
.addReg(RISCV::X0, RegState::Define | RegState::Dead)
.addReg(AVLReg)
.addImm(Info.encodeVTYPE());
- if (LIS) {
- LIS->InsertMachineInstrInMaps(*MI);
- // Normally the AVL's live range will already extend past the inserted
- // vsetvli because the pseudos below will already use the AVL. But this
- // isn't always the case, e.g. PseudoVMV_X_S doesn't have an AVL operand.
- LIS->getInterval(AVLReg).extendInBlock(
- LIS->getMBBStartIdx(&MBB), LIS->getInstructionIndex(*MI).getRegSlot());
- }
+ LIS->InsertMachineInstrInMaps(*MI);
+ // Normally the AVL's live range will already extend past the inserted vsetvli
+ // because the pseudos below will already use the AVL. But this isn't always
+ // the case, e.g. PseudoVMV_X_S doesn't have an AVL operand.
+ LIS->getInterval(AVLReg).extendInBlock(
+ LIS->getMBBStartIdx(&MBB), LIS->getInstructionIndex(*MI).getRegSlot());
}
/// Return true if a VSETVLI is required to transition from CurInfo to Require
@@ -1264,14 +1230,10 @@ void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info,
if (RISCV::isFaultFirstLoad(MI)) {
// Update AVL to vl-output of the fault first load.
assert(MI.getOperand(1).getReg().isVirtual());
- if (LIS) {
- auto &LI = LIS->getInterval(MI.getOperand(1).getReg());
- SlotIndex SI =
- LIS->getSlotIndexes()->getInstructionIndex(MI).getRegSlot();
- VNInfo *VNI = LI.getVNInfoAt(SI);
- Info.setAVLRegDef(VNI, MI.getOperand(1).getReg());
- } else
- Info.setAVLRegDef(nullptr, MI.getOperand(1).getReg());
+ auto &LI = LIS->getInterval(MI.getOperand(1).getReg());
+ SlotIndex SI = LIS->getSlotIndexes()->getInstructionIndex(MI).getRegSlot();
+ VNInfo *VNI = LI.getVNInfoAt(SI);
+ Info.setAVLRegDef(VNI, MI.getOperand(1).getReg());
return;
}
@@ -1365,9 +1327,6 @@ bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require,
if (!Require.hasAVLReg())
return true;
- if (!LIS)
- return true;
-
// We need the AVL to have been produced by a PHI node in this basic block.
const VNInfo *Valno = Require.getAVLVNInfo();
if (!Valno->isPHIDef() || LIS->getMBBFromIndex(Valno->def) != &MBB)
@@ -1443,29 +1402,27 @@ void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) {
MachineOperand &VLOp = MI.getOperand(getVLOpNum(MI));
if (VLOp.isReg()) {
Register Reg = VLOp.getReg();
+ LiveInterval &LI = LIS->getInterval(Reg);
// Erase the AVL operand from the instruction.
VLOp.setReg(RISCV::NoRegister);
VLOp.setIsKill(false);
- if (LIS) {
- LiveInterval &LI = LIS->getInterval(Reg);
- SmallVector<MachineInstr *> DeadMIs;
- LIS->shrinkToUses(&LI, &DeadMIs);
- // We might have separate components that need split due to
- // needVSETVLIPHI causing us to skip inserting a new VL def.
- SmallVector<LiveInterval *> SplitLIs;
- LIS->splitSeparateComponents(LI, SplitLIs);
-
- // If the AVL was an immediate > 31, then it would have been emitted
- // as an ADDI. However, the ADDI might not have been used in the
- // vsetvli, or a vsetvli might not have been emitted, so it may be
- // dead now.
- for (MachineInstr *DeadMI : DeadMIs) {
- if (!TII->isAddImmediate(*DeadMI, Reg))
- continue;
- LIS->RemoveMachineInstrFromMaps(*DeadMI);
- DeadMI->eraseFromParent();
- }
+ SmallVector<MachineInstr *> DeadMIs;
+ LIS->shrinkToUses(&LI, &DeadMIs);
+ // We might have separate components that need split due to
+ // needVSETVLIPHI causing us to skip inserting a new VL def.
+ SmallVector<LiveInterval *> SplitLIs;
+ LIS->splitSeparateComponents(LI, SplitLIs);
+
+ // If the AVL was an immediate > 31, then it would have been emitted
+ // as an ADDI. However, the ADDI might not have been used in the
+ // vsetvli, or a vsetvli might not have been emitted, so it may be
+ // dead now.
+ for (MachineInstr *DeadMI : DeadMIs) {
+ if (!TII->isAddImmediate(*DeadMI, Reg))
+ continue;
+ LIS->RemoveMachineInstrFromMaps(*DeadMI);
+ DeadMI->eraseFromParent();
}
}
MI.addOperand(MachineOperand::CreateReg(RISCV::VL, /*isDef*/ false,
@@ -1522,9 +1479,6 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
if (!UnavailablePred || !AvailableInfo.isValid())
return;
- if (!LIS)
- return;
-
// If we don't know the exact VTYPE, we can't copy the vsetvli to the exit of
// the unavailable pred.
if (AvailableInfo.hasSEWLMULRatioOnly())
@@ -1671,7 +1625,7 @@ void RISCVInsertVSETVLI::coalesceVSETVLIs(MachineBasicBlock &MBB) const {
// The def of DefReg moved to MI, so extend the LiveInterval up to
// it.
- if (DefReg.isVirtual() && LIS) {
+ if (DefReg.isVirtual()) {
LiveInterval &DefLI = LIS->getInterval(DefReg);
SlotIndex MISlot = LIS->getInstructionIndex(MI).getRegSlot();
VNInfo *DefVNI = DefLI.getVNInfoAt(DefLI.beginIndex());
@@ -1700,15 +1654,13 @@ void RISCVInsertVSETVLI::coalesceVSETVLIs(MachineBasicBlock &MBB) const {
if (OldVLReg && OldVLReg.isVirtual()) {
// NextMI no longer uses OldVLReg so shrink its LiveInterval.
- if (LIS)
- LIS->shrinkToUses(&LIS->getInterval(OldVLReg));
+ LIS->shrinkToUses(&LIS->getInterval(OldVLReg));
MachineInstr *VLOpDef = MRI->getUniqueVRegDef(OldVLReg);
if (VLOpDef && TII->isAddImmediate(*VLOpDef, OldVLReg) &&
MRI->use_nodbg_empty(OldVLReg)) {
VLOpDef->eraseFromParent();
- if (LIS)
- LIS->removeInterval(OldVLReg);
+ LIS->removeInterval(OldVLReg);
}
}
MI.setDesc(NextMI->getDesc());
@@ -1724,8 +1676,7 @@ void RISCVInsertVSETVLI::coalesceVSETVLIs(MachineBasicBlock &MBB) const {
NumCoalescedVSETVL += ToDelete.size();
for (auto *MI : ToDelete) {
- if (LIS)
- LIS->RemoveMachineInstrFromMaps(*MI);
+ LIS->RemoveMachineInstrFromMaps(*MI);
MI->eraseFromParent();
}
}
@@ -1740,14 +1691,12 @@ void RISCVInsertVSETVLI::insertReadVL(MachineBasicBlock &MBB) {
auto ReadVLMI = BuildMI(MBB, I, MI.getDebugLoc(),
TII->get(RISCV::PseudoReadVL), VLOutput);
// Move the LiveInterval's definition down to PseudoReadVL.
- if (LIS) {
- SlotIndex NewDefSI =
- LIS->InsertMachineInstrInMaps(*ReadVLMI).getRegSlot();
- LiveInterval &DefLI = LIS->getInterval(VLOutput);
- VNInfo *DefVNI = DefLI.getVNInfoAt(DefLI.beginIndex());
- DefLI.removeSegment(DefLI.beginIndex(), NewDefSI);
- DefVNI->def = NewDefSI;
- }
+ SlotIndex NewDefSI =
+ LIS->InsertMachineInstrInMaps(*ReadVLMI).getRegSlot();
+ LiveInterval &DefLI = LIS->getInterval(VLOutput);
+ VNInfo *DefVNI = DefLI.getVNInfoAt(DefLI.beginIndex());
+ DefLI.removeSegment(DefLI.beginIndex(), NewDefSI);
+ DefVNI->def = NewDefSI;
}
// We don't use the vl output of the VLEFF/VLSEGFF anymore.
MI.getOperand(1).setReg(RISCV::X0);
@@ -1765,7 +1714,7 @@ bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) {
TII = ST->getInstrInfo();
MRI = &MF.getRegInfo();
- LIS = getAnalysisIfAvailable<LiveIntervals>();
+ LIS = &getAnalysis<LiveIntervals>();
assert(BlockInfo.empty() && "Expect empty block infos");
BlockInfo.resize(MF.getNumBlockIDs());
diff --git a/llvm/test/CodeGen/RISCV/O0-pipeline.ll b/llvm/test/CodeGen/RISCV/O0-pipeline.ll
index 953eb873b660b..ec49ed302d49d 100644
--- a/llvm/test/CodeGen/RISCV/O0-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O0-pipeline.ll
@@ -47,6 +47,9 @@
; CHECK-NEXT: Eliminate PHI nodes for register allocation
; CHECK-NEXT: Two-Address instruction pass
; CHECK-NEXT: Fast Register Allocator
+; CHECK-NEXT: MachineDominator Tree Construction
+; CHECK-NEXT: Slot index numbering
+; CHECK-NEXT: Live Interval Analysis
; CHECK-NEXT: RISC-V Insert VSETVLI pass
; CHECK-NEXT: Fast Register Allocator
; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis
diff --git a/llvm/test/CodeGen/RISCV/rvv/pr93587.ll b/llvm/test/CodeGen/RISCV/rvv/pr93587.ll
deleted file mode 100644
index 1c2923a2de893..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/pr93587.ll
+++ /dev/null
@@ -1,37 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=riscv64 -O0 < %s | FileCheck %s
-
-; Make sure we don't run LiveIntervals at O0, otherwise it will crash when
-; running on this unreachable block.
-
-define i16 @f() {
-; CHECK-LABEL: f:
-; CHECK: # %bb.0: # %BB
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: j .LBB0_1
-; CHECK-NEXT: .LBB0_1: # %BB1
-; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: li a0, 0
-; CHECK-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; CHECK-NEXT: j .LBB0_1
-; CHECK-NEXT: # %bb.2: # %BB1
-; CHECK-NEXT: li a0, 0
-; CHECK-NEXT: bnez a0, .LBB0_1
-; CHECK-NEXT: j .LBB0_3
-; CHECK-NEXT: .LBB0_3: # %BB2
-; CHECK-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-BB:
- br label %BB1
-
-BB1:
- %A = or i16 0, 0
- %B = fcmp true float 0.000000e+00, 0.000000e+00
- %C = or i1 %B, false
- br i1 %C, label %BB1, label %BB2
-
-BB2:
- ret i16 %A
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-O0.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-O0.ll
index 33acfb7dceb94..aef18fcd06cd6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-O0.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-O0.ll
@@ -54,12 +54,10 @@ define <vscale x 1 x double> @intrinsic_same_vlmax(<vscale x 1 x double> %a, <vs
; CHECK-LABEL: intrinsic_same_vlmax:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, ma
; CHECK-NEXT: # implicit-def: $v9
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: vfadd.vv v9, v8, v10
; CHECK-NEXT: # implicit-def: $v8
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: vfadd.vv v8, v9, v10
; CHECK-NEXT: ret
entry:
@@ -82,12 +80,10 @@ define <vscale x 1 x double> @intrinsic_same_avl_imm(<vscale x 1 x double> %a, <
; CHECK-LABEL: intrinsic_same_avl_imm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vsetivli a0, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli a0, 2, e64, m1, tu, ma
; CHECK-NEXT: # implicit-def: $v9
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: vfadd.vv v9, v8, v10
; CHECK-NEXT: # implicit-def: $v8
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: vfadd.vv v8, v9, v10
; CHECK-NEXT: ret
entry:
@@ -109,12 +105,10 @@ define <vscale x 1 x double> @intrinsic_same_avl_reg(i64 %avl, <vscale x 1 x dou
; CHECK-LABEL: intrinsic_same_avl_reg:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vsetvli a0, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, a0, e64, m1, tu, ma
; CHECK-NEXT: # implicit-def: $v9
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: vfadd.vv v9, v8, v10
; CHECK-NEXT: # implicit-def: $v8
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: vfadd.vv v8, v9, v10
; CHECK-NEXT: ret
entry:
@@ -136,13 +130,11 @@ define <vscale x 1 x double> @intrinsic_
diff _avl_reg(i64 %avl, i64 %avl2, <vscal
; CHECK-LABEL: intrinsic_
diff _avl_reg:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vsetvli a0, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, a0, e64, m1, tu, ma
; CHECK-NEXT: # implicit-def: $v9
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: vfadd.vv v9, v8, v10
-; CHECK-NEXT: vsetvli a0, a1, e32, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, a1, e64, m1, tu, ma
; CHECK-NEXT: # implicit-def: $v8
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: vfadd.vv v8, v9, v10
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
index 681b50de5b81c..a4b374c8bb401 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc %s -o - -mtriple=riscv64 -mattr=v -run-pass=liveintervals,riscv-insert-vsetvli \
+# RUN: llc %s -o - -mtriple=riscv64 -mattr=v -run-pass=riscv-insert-vsetvli \
# RUN: | FileCheck %s
--- |
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